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[WebAssembly] Support fp reg class in r constraint

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Patch by snek

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D90978
This commit is contained in:
snek 2020-11-18 10:23:01 -08:00 committed by Heejin Ahn
parent 0fadcfd431
commit a27ae8bd58
2 changed files with 36 additions and 0 deletions
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10
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
View File

@ -563,6 +563,16 @@ WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
if (VT.getSizeInBits() <= 64)
return std::make_pair(0U, &WebAssembly::I64RegClass);
}
if (VT.isFloatingPoint() && !VT.isVector()) {
switch (VT.getSizeInBits()) {
case 32:
return std::make_pair(0U, &WebAssembly::F32RegClass);
case 64:
return std::make_pair(0U, &WebAssembly::F64RegClass);
default:
break;
}
}
break;
default:
break;

26
test/CodeGen/WebAssembly/inline-asm.ll
View File

@ -46,6 +46,32 @@ entry:
ret i64 %0
}
; CHECK-LABEL: foo_float:
; CHECK-NEXT: .functype foo_float (f32) -> (f32){{$}}
; CHECK-NEXT: #APP{{$}}
; CHECK-NEXT: # 0 = aaa(0){{$}}
; CHECK-NEXT: #NO_APP{{$}}
; CHECK-NEXT: local.get $push0=, 0{{$}}
; CHECK-NEXT: return $pop0{{$}}
define float @foo_float(float %r) {
entry:
%0 = tail call float asm sideeffect "# $0 = aaa($1)", "=r,r"(float %r) #0, !srcloc !0
ret float %0
}
; CHECK-LABEL: foo_double:
; CHECK-NEXT: .functype foo_double (f64) -> (f64){{$}}
; CHECK-NEXT: #APP{{$}}
; CHECK-NEXT: # 0 = aaa(0){{$}}
; CHECK-NEXT: #NO_APP{{$}}
; CHECK-NEXT: local.get $push0=, 0{{$}}
; CHECK-NEXT: return $pop0{{$}}
define double @foo_double(double %r) {
entry:
%0 = tail call double asm sideeffect "# $0 = aaa($1)", "=r,r"(double %r) #0, !srcloc !0
ret double %0
}
; CHECK-LABEL: X_i16:
; CHECK: foo 1{{$}}
; CHECK: local.get $push[[S0:[0-9]+]]=, 0{{$}}