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[DAGCombiner] eliminate shuffle of insert element
I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either repeating a scalar insertion at the same position in a vector or translated to a different element index. Like the earlier patch, this could be an instcombine too, but since we opted to make this a DAG transform earlier, I've made this one a DAG patch too. We do not need any legality checking because the new insert is identical to the existing insert except that it may have a different constant insertion operand. The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the motivation for D38756. Differential Revision: https://reviews.llvm.org/D40209 llvm-svn: 320050
This commit is contained in:
Sanjay Patel
parent
f90ff6307d
commit
a2ab5a7248
@ -15728,6 +15728,84 @@ static SDValue combineShuffleOfSplat(ArrayRef<int> UserMask,
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NewMask);
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}
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/// If the shuffle mask is taking exactly one element from the first vector
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/// operand and passing through all other elements from the second vector
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/// operand, return the index of the mask element that is choosing an element
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/// from the first operand. Otherwise, return -1.
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static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1(ArrayRef<int> Mask) {
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int MaskSize = Mask.size();
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int EltFromOp0 = -1;
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// TODO: This does not match if there are undef elements in the shuffle mask.
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// Should we ignore undefs in the shuffle mask instead? The trade-off is
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// removing an instruction (a shuffle), but losing the knowledge that some
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// vector lanes are not needed.
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for (int i = 0; i != MaskSize; ++i) {
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if (Mask[i] >= 0 && Mask[i] < MaskSize) {
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// We're looking for a shuffle of exactly one element from operand 0.
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if (EltFromOp0 != -1)
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return -1;
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EltFromOp0 = i;
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} else if (Mask[i] != i + MaskSize) {
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// Nothing from operand 1 can change lanes.
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return -1;
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}
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}
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return EltFromOp0;
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}
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/// If a shuffle inserts exactly one element from a source vector operand into
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/// another vector operand and we can access the specified element as a scalar,
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/// then we can eliminate the shuffle.
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static SDValue replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf,
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SelectionDAG &DAG) {
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// First, check if we are taking one element of a vector and shuffling that
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// element into another vector.
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ArrayRef<int> Mask = Shuf->getMask();
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SmallVector<int, 16> CommutedMask(Mask.begin(), Mask.end());
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SDValue Op0 = Shuf->getOperand(0);
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SDValue Op1 = Shuf->getOperand(1);
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int ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(Mask);
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if (ShufOp0Index == -1) {
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// Commute mask and check again.
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ShuffleVectorSDNode::commuteMask(CommutedMask);
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ShufOp0Index = getShuffleMaskIndexOfOneElementFromOp0IntoOp1(CommutedMask);
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if (ShufOp0Index == -1)
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return SDValue();
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// Commute operands to match the commuted shuffle mask.
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std::swap(Op0, Op1);
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Mask = CommutedMask;
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}
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// The shuffle inserts exactly one element from operand 0 into operand 1.
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// Now see if we can access that element as a scalar via a real insert element
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// instruction.
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// TODO: We can try harder to locate the element as a scalar. Examples: it
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// could be an operand of SCALAR_TO_VECTOR, BUILD_VECTOR, or a constant.
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assert(Mask[ShufOp0Index] >= 0 && Mask[ShufOp0Index] < (int)Mask.size() &&
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"Shuffle mask value must be from operand 0");
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if (Op0.getOpcode() != ISD::INSERT_VECTOR_ELT)
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return SDValue();
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auto *InsIndexC = dyn_cast<ConstantSDNode>(Op0.getOperand(2));
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if (!InsIndexC || InsIndexC->getSExtValue() != Mask[ShufOp0Index])
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return SDValue();
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// There's an existing insertelement with constant insertion index, so we
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// don't need to check the legality/profitability of a replacement operation
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// that differs at most in the constant value. The target should be able to
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// lower any of those in a similar way. If not, legalization will expand this
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// to a scalar-to-vector plus shuffle.
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//
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// Note that the shuffle may move the scalar from the position that the insert
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// element used. Therefore, our new insert element occurs at the shuffle's
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// mask index value, not the insert's index value.
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// shuffle (insertelt v1, x, C), v2, mask --> insertelt v2, x, C'
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SDValue NewInsIndex = DAG.getConstant(ShufOp0Index, SDLoc(Shuf),
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Op0.getOperand(2).getValueType());
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Shuf), Op0.getValueType(),
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Op1, Op0.getOperand(1), NewInsIndex);
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}
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SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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EVT VT = N->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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@ -15778,6 +15856,9 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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if (SDValue V = simplifyShuffleMask(SVN, N0, N1, DAG))
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return V;
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if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG))
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return InsElt;
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// A shuffle of a single vector that is a splat can always be folded.
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if (auto *N0Shuf = dyn_cast<ShuffleVectorSDNode>(N0))
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if (N1->isUndef() && N0Shuf->isSplat())
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@ -13,14 +13,13 @@ define <4 x i32> @ins_elt_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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;
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; SSE4-LABEL: ins_elt_0:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $0, %edi, %xmm0
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; SSE4-NEXT: pinsrd $0, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; AVX-NEXT: vpinsrd $0, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 0
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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@ -30,23 +29,20 @@ define <4 x i32> @ins_elt_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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define <4 x i32> @ins_elt_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_1:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $1, %edi, %xmm0
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
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; SSE4-NEXT: pinsrd $1, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
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; AVX-NEXT: vpinsrd $1, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 1
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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@ -58,24 +54,21 @@ define <4 x i32> @ins_elt_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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define <4 x i32> @ins_elt_2_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_2_commute:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_2_commute:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $2, %edi, %xmm0
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
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; SSE4-NEXT: pinsrd $2, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_2_commute:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $2, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
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; AVX-NEXT: vpinsrd $2, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 2
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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@ -85,24 +78,21 @@ define <4 x i32> @ins_elt_2_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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define <4 x i32> @ins_elt_3_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_3_commute:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_3_commute:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $3, %edi, %xmm0
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
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; SSE4-NEXT: pinsrd $3, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_3_commute:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
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; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 3
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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@ -122,16 +112,13 @@ define <4 x i32> @ins_elt_0_to_2(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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;
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; SSE4-LABEL: ins_elt_0_to_2:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $0, %edi, %xmm0
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; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
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; SSE4-NEXT: pinsrd $2, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_0_to_2:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
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; AVX-NEXT: vpinsrd $2, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 0
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
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@ -148,16 +135,13 @@ define <4 x i32> @ins_elt_1_to_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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;
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; SSE4-LABEL: ins_elt_1_to_0:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $1, %edi, %xmm0
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; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; SSE4-NEXT: pinsrd $0, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_1_to_0:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; AVX-NEXT: vpinsrd $0, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 1
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%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
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@ -167,26 +151,21 @@ define <4 x i32> @ins_elt_1_to_0(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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define <4 x i32> @ins_elt_2_to_3(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_2_to_3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,0]
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; SSE2-NEXT: movd %edi, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: ins_elt_2_to_3:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pinsrd $2, %edi, %xmm0
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; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
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; SSE4-NEXT: pinsrd $3, %edi, %xmm1
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; SSE4-NEXT: movdqa %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX-LABEL: ins_elt_2_to_3:
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; AVX: # %bb.0:
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; AVX-NEXT: vpinsrd $2, %edi, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
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; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0
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; AVX-NEXT: retq
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%ins = insertelement <4 x i32> %v1, i32 %x, i32 2
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%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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@ -196,25 +175,20 @@ define <4 x i32> @ins_elt_2_to_3(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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define <4 x i32> @ins_elt_3_to_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
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; SSE2-LABEL: ins_elt_3_to_1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movd %edi, %xmm2
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[2,0]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[0,0]
|
||||
; SSE2-NEXT: movd %edi, %xmm0
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE4-LABEL: ins_elt_3_to_1:
|
||||
; SSE4: # %bb.0:
|
||||
; SSE4-NEXT: pinsrd $3, %edi, %xmm0
|
||||
; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
|
||||
; SSE4-NEXT: pinsrd $1, %edi, %xmm1
|
||||
; SSE4-NEXT: movdqa %xmm1, %xmm0
|
||||
; SSE4-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: ins_elt_3_to_1:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
|
||||
; AVX-NEXT: vpinsrd $1, %edi, %xmm1, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%ins = insertelement <4 x i32> %v1, i32 %x, i32 3
|
||||
%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
|
||||
|
||||
@ -391,16 +391,12 @@ define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
|
||||
; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
|
||||
; X32: ## %bb.0:
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
|
||||
; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
|
||||
; X32-NEXT: pinsrd $2, (%eax), %xmm0
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
|
||||
; X64: ## %bb.0:
|
||||
; X64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
|
||||
; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
|
||||
; X64-NEXT: pinsrd $2, (%rdi), %xmm0
|
||||
; X64-NEXT: retq
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%2 = insertelement <4 x i32> undef, i32 %1, i32 0
|
||||
|
||||
@ -1063,27 +1063,13 @@ define <2 x i64> @insert_reg_lo_v2i64(i64 %a, <2 x i64> %b) {
|
||||
;
|
||||
; SSE41-LABEL: insert_reg_lo_v2i64:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movq %rdi, %xmm1
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; SSE41-NEXT: pinsrq $0, %rdi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: insert_reg_lo_v2i64:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_reg_lo_v2i64:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_reg_lo_v2i64:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
; AVX-LABEL: insert_reg_lo_v2i64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%v = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
%shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 0, i32 3>
|
||||
ret <2 x i64> %shuffle
|
||||
@ -1107,27 +1093,13 @@ define <2 x i64> @insert_mem_lo_v2i64(i64* %ptr, <2 x i64> %b) {
|
||||
;
|
||||
; SSE41-LABEL: insert_mem_lo_v2i64:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; SSE41-NEXT: pinsrq $0, (%rdi), %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: insert_mem_lo_v2i64:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: insert_mem_lo_v2i64:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: insert_mem_lo_v2i64:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX512VL-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
||||
; AVX512VL-NEXT: retq
|
||||
; AVX-LABEL: insert_mem_lo_v2i64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpinsrq $0, (%rdi), %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%a = load i64, i64* %ptr
|
||||
%v = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
%shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 0, i32 3>
|
||||
@ -1135,16 +1107,32 @@ define <2 x i64> @insert_mem_lo_v2i64(i64* %ptr, <2 x i64> %b) {
|
||||
}
|
||||
|
||||
define <2 x i64> @insert_reg_hi_v2i64(i64 %a, <2 x i64> %b) {
|
||||
; SSE-LABEL: insert_reg_hi_v2i64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: movq %rdi, %xmm1
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE-NEXT: retq
|
||||
; SSE2-LABEL: insert_reg_hi_v2i64:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movq %rdi, %xmm1
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE3-LABEL: insert_reg_hi_v2i64:
|
||||
; SSE3: # %bb.0:
|
||||
; SSE3-NEXT: movq %rdi, %xmm1
|
||||
; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE3-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: insert_reg_hi_v2i64:
|
||||
; SSSE3: # %bb.0:
|
||||
; SSSE3-NEXT: movq %rdi, %xmm1
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: insert_reg_hi_v2i64:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: pinsrq $1, %rdi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: insert_reg_hi_v2i64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovq %rdi, %xmm1
|
||||
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%v = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
%shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 2, i32 0>
|
||||
@ -1152,16 +1140,32 @@ define <2 x i64> @insert_reg_hi_v2i64(i64 %a, <2 x i64> %b) {
|
||||
}
|
||||
|
||||
define <2 x i64> @insert_mem_hi_v2i64(i64* %ptr, <2 x i64> %b) {
|
||||
; SSE-LABEL: insert_mem_hi_v2i64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE-NEXT: retq
|
||||
; SSE2-LABEL: insert_mem_hi_v2i64:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE3-LABEL: insert_mem_hi_v2i64:
|
||||
; SSE3: # %bb.0:
|
||||
; SSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE3-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: insert_mem_hi_v2i64:
|
||||
; SSSE3: # %bb.0:
|
||||
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: insert_mem_hi_v2i64:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: pinsrq $1, (%rdi), %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: insert_mem_hi_v2i64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: vpinsrq $1, (%rdi), %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%a = load i64, i64* %ptr
|
||||
%v = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
|
||||
@ -2759,21 +2759,15 @@ define <4 x i32> @combine_constant_insertion_v4i32(i32 %f) {
|
||||
;
|
||||
; SSE41-LABEL: combine_constant_insertion_v4i32:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movd %edi, %xmm0
|
||||
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <u,4,5,30>
|
||||
; SSE41-NEXT: pinsrd $0, %edi, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_constant_insertion_v4i32:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vmovd %edi, %xmm0
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],mem[2,3,4,5,6,7]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_constant_insertion_v4i32:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vmovd %edi, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]
|
||||
; AVX2-NEXT: retq
|
||||
; AVX-LABEL: combine_constant_insertion_v4i32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <u,4,5,30>
|
||||
; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%a0 = insertelement <4 x i32> undef, i32 %f, i32 0
|
||||
%ret = shufflevector <4 x i32> %a0, <4 x i32> <i32 undef, i32 4, i32 5, i32 30>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
|
||||
ret <4 x i32> %ret
|
||||
|
||||
Loading…
Reference in New Issue
Block a user