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[X86] Remove unnecessary MMX reg-mem InstRW scheduler overrides.

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llvm-svn: 330581
This commit is contained in:
Simon Pilgrim 2018-04-23 11:57:15 +00:00
parent d2dd32f947
commit a2c00eb146
6 changed files with 9 additions and 122 deletions
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43
lib/Target/X86/X86SchedBroadwell.td
View File

@ -951,15 +951,7 @@ def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
"MMX_PSLLQrm",
"MMX_PSLLWrm",
"MMX_PSRADrm",
"MMX_PSRAWrm",
"MMX_PSRLDrm",
"MMX_PSRLQrm",
"MMX_PSRLWrm",
"VCVTPH2PS(Y?)rm",
def: InstRW<[BWWriteResGroup59], (instregex "VCVTPH2PS(Y?)rm",
"(V?)CVTPS2PDrm",
"(V?)CVTSS2SDrm",
"VPSLLVQrm",
@ -983,16 +975,7 @@ def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
"(V?)INSERTPSrm",
def: InstRW<[BWWriteResGroup61], (instregex "(V?)INSERTPSrm",
"(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
@ -1057,18 +1040,6 @@ def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
"MMX_PADD(B|D|Q|W)irm",
"MMX_PADDS(B|W)irm",
"MMX_PADDUS(B|W)irm",
"MMX_PAVG(B|W)irm",
"MMX_PCMPEQ(B|D|W)irm",
"MMX_PCMPGT(B|D|W)irm",
"MMX_P(MAX|MIN)SWirm",
"MMX_P(MAX|MIN)UBirm",
"MMX_PSIGN(B|D|W)rm",
"MMX_PSUB(B|D|Q|W)irm",
"MMX_PSUBS(B|W)irm",
"MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm",
"(V?)PABSBrm",
"(V?)PABSDrm",
@ -1679,15 +1650,7 @@ def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
"MMX_PMADDWDirm",
"MMX_PMULHRSWrm",
"MMX_PMULHUWirm",
"MMX_PMULHWirm",
"MMX_PMULLWirm",
"MMX_PMULUDQirm",
"MMX_PSADBWirm",
"(V?)PCMPGTQrm",
def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm",
"(V?)PHMINPOSUWrm",
"(V?)PMADDUBSWrm",
"(V?)PMADDWDrm",

43
lib/Target/X86/X86SchedHaswell.td
View File

@ -781,15 +781,7 @@ def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm",
"MMX_PSLLQrm",
"MMX_PSLLWrm",
"MMX_PSRADrm",
"MMX_PSRAWrm",
"MMX_PSRLDrm",
"MMX_PSRLQrm",
"MMX_PSRLWrm",
"VCVTPH2PSrm",
def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm",
"(V?)CVTPS2PDrm")>;
def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
@ -944,16 +936,7 @@ def HWWriteResGroup13_2 : SchedWriteRes<[HWPort5,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
"(V?)MOVHPDrm",
def: InstRW<[HWWriteResGroup13_2], (instregex "(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
@ -990,18 +973,6 @@ def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
"MMX_PADD(B|D|Q|W)irm",
"MMX_PADDS(B|W)irm",
"MMX_PADDUS(B|W)irm",
"MMX_PAVG(B|W)irm",
"MMX_PCMPEQ(B|D|W)irm",
"MMX_PCMPGT(B|D|W)irm",
"MMX_P(MAX|MIN)SWirm",
"MMX_P(MAX|MIN)UBirm",
"MMX_PSIGN(B|D|W)rm",
"MMX_PSUB(B|D|Q|W)irm",
"MMX_PSUBS(B|W)irm",
"MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm")>;
def HWWriteResGroup16_1 : SchedWriteRes<[HWPort23,HWPort15]> {
@ -1953,15 +1924,7 @@ def HWWriteResGroup91 : SchedWriteRes<[HWPort0,HWPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup91], (instregex "MMX_PMADDUBSWrm",
"MMX_PMADDWDirm",
"MMX_PMULHRSWrm",
"MMX_PMULHUWirm",
"MMX_PMULHWirm",
"MMX_PMULLWirm",
"MMX_PMULUDQirm",
"MMX_PSADBWirm",
"(V?)RCPSSm",
def: InstRW<[HWWriteResGroup91], (instregex "(V?)RCPSSm",
"(V?)RSQRTSSm")>;
def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {

1
lib/Target/X86/X86SchedSandyBridge.td
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@ -904,7 +904,6 @@ def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
}
def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
"MMX_PALIGNRrmi",
"MMX_PSHUFBrm",
"MMX_PSIGN(B|D|W)rm")>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {

20
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -1131,14 +1131,6 @@ def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
"MMX_PMAXUBirm",
"MMX_PMINSWirm",
"MMX_PMINUBirm",
"MMX_PSLLDrm",
"MMX_PSLLQrm",
"MMX_PSLLWrm",
"MMX_PSRADrm",
"MMX_PSRAWrm",
"MMX_PSRLDrm",
"MMX_PSRLQrm",
"MMX_PSRLWrm",
"MMX_PSUBSBirm",
"MMX_PSUBSWirm",
"MMX_PSUBUSBirm",
@ -1161,16 +1153,7 @@ def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
"(V?)MOVHPDrm",
def: InstRW<[SKLWriteResGroup71], (instregex "(V?)MOVHPDrm",
"(V?)MOVHPSrm",
"(V?)MOVLPDrm",
"(V?)MOVLPSrm",
@ -1578,7 +1561,6 @@ def: InstRW<[SKLWriteResGroup108], (instregex "FCOM32m",
"FCOM64m",
"FCOMP32m",
"FCOMP64m",
"MMX_PSADBWirm",
"VPACKSSDWYrm",
"VPACKSSWBYrm",
"VPACKUSDWYrm",

19
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -2260,14 +2260,6 @@ def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm",
"MMX_PMAXUBirm",
"MMX_PMINSWirm",
"MMX_PMINUBirm",
"MMX_PSLLDrm",
"MMX_PSLLQrm",
"MMX_PSLLWrm",
"MMX_PSRADrm",
"MMX_PSRAWrm",
"MMX_PSRLDrm",
"MMX_PSRLQrm",
"MMX_PSRLWrm",
"MMX_PSUBSBirm",
"MMX_PSUBSWirm",
"MMX_PSUBUSBirm",
@ -2308,16 +2300,7 @@ def SKXWriteResGroup75 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
"MOVHPDrm",
def: InstRW<[SKXWriteResGroup75], (instregex "MOVHPDrm",
"MOVHPSrm",
"MOVLPDrm",
"MOVLPSrm",

5
lib/Target/X86/X86ScheduleAtom.td
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@ -320,10 +320,7 @@ def : InstRW<[AtomWrite0_1], (instrs FXAM,
def : InstRW<[AtomWrite0_1], (instregex "(ADC|ADD|AND|NEG|NOT|OR|SBB|SUB|XOR)(8|16|32|64)m",
"(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
"MOV(S|Z)X(32|64)rr(8|8_NOREX|16)",
"LD_F(P)?(16|32|64)?(m|rr)",
"MMX_PAVG(B|W)irm",
"MMX_P(MAX|MIN)(UB|SW)irm",
"MMX_PSIGN(B|D|W)rm")>;
"LD_F(P)?(16|32|64)?(m|rr)")>;
def AtomWrite0_3 : SchedWriteRes<[AtomPort0]> {
let Latency = 3;