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[mips] Modify definitions of floating point branch instructions.
No functionality change. llvm-svn: 170076
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@ -273,6 +273,17 @@ class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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!strconcat(opstr, "\t$fs, ${index}(${base})"),
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[(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>;
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class BC1F_FT<string opstr, InstrItinClass Itin,
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SDPatternOperator Op = null_frag> :
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InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
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[(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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let Uses = [FCR31];
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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@ -495,8 +506,8 @@ let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
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}
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let DecoderMethod = "DecodeBC1" in {
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def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">;
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def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">;
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def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
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def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Flag Conditions
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@ -453,3 +453,16 @@ class SWXC1_FM<bits<6> funct> {
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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class BC1F_FM<bit nd, bit tf> {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = 0x8;
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let Inst{20-18} = 0; // cc
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let Inst{17} = nd;
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let Inst{16} = tf;
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let Inst{15-0} = offset;
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}
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