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LiveIntervalAnalysis: Cleanup; NFC
- Fix doxygen comments: Do not repeat name, remove duplicated doxygen comment (on declaration + implementation), etc. - Use more range based for llvm-svn: 292455
This commit is contained in:
Matthias Braun
parent
dff5eed453
commit
a2f54981f9
@ -7,13 +7,13 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' and there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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/// \file This file implements the LiveInterval analysis pass. Given some
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/// numbering of each the machine instructions (in this implemention depth-first
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/// order) an interval [i, j) is said to be a live interval for register v if
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/// there is no instruction with number j' > j such that v is live at j' and
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/// there is no instruction with number i' < i such that v is live at i'. In
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/// this implementation intervals can have holes, i.e. an interval might look
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/// like [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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@ -60,20 +60,17 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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LiveRangeCalc *LRCalc;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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VNInfo::Allocator VNInfoAllocator;
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/// Live interval pointers for all the virtual registers.
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IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
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/// RegMaskSlots - Sorted list of instructions with register mask operands.
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/// Always use the 'r' slot, RegMasks are normal clobbers, not early
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/// clobbers.
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/// Sorted list of instructions with register mask operands. Always use the
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/// 'r' slot, RegMasks are normal clobbers, not early clobbers.
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SmallVector<SlotIndex, 8> RegMaskSlots;
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/// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
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/// pointer to the corresponding register mask. This pointer can be
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/// recomputed as:
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/// This vector is parallel to RegMaskSlots, it holds a pointer to the
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/// corresponding register mask. This pointer can be recomputed as:
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///
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/// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
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/// unsigned OpNum = findRegMaskOperand(MI);
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@ -97,11 +94,11 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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SmallVector<LiveRange*, 0> RegUnitRanges;
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public:
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static char ID; // Pass identification, replacement for typeid
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static char ID;
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LiveIntervals();
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~LiveIntervals() override;
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// Calculate the spill weight to assign to a single instruction.
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/// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse,
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const MachineBlockFrequencyInfo *MBFI,
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const MachineInstr &Instr);
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@ -121,7 +118,7 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
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}
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// Interval creation.
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/// Interval creation.
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LiveInterval &createEmptyInterval(unsigned Reg) {
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assert(!hasInterval(Reg) && "Interval already exists!");
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VirtRegIntervals.grow(Reg);
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@ -135,7 +132,7 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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return LI;
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}
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// Interval removal.
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/// Interval removal.
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void removeInterval(unsigned Reg) {
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delete VirtRegIntervals[Reg];
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VirtRegIntervals[Reg] = nullptr;
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@ -163,16 +160,16 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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/// LiveInterval::removeEmptySubranges() afterwards.
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void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
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/// Extend the live range @p LR to reach all points in @p Indices. The
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/// points in the @p Indices array must be jointly dominated by the union
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/// of the existing defs in @p LR and points in @p Undefs.
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/// Extend the live range \p LR to reach all points in \p Indices. The
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/// points in the \p Indices array must be jointly dominated by the union
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/// of the existing defs in \p LR and points in \p Undefs.
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///
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/// PHI-defs are added as needed to maintain SSA form.
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///
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/// If a SlotIndex in @p Indices is the end index of a basic block, @p LR
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/// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
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/// will be extended to be live out of the basic block.
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/// If a SlotIndex in @p Indices is jointy dominated only by points in
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/// @p Undefs, the live range will not be extended to that point.
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/// If a SlotIndex in \p Indices is jointy dominated only by points in
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/// \p Undefs, the live range will not be extended to that point.
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///
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/// See also LiveRangeCalc::extend().
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void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
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@ -182,7 +179,7 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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extendToIndices(LR, Indices, /*Undefs=*/{});
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}
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/// If @p LR has a live value at @p Kill, prune its live range by removing
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/// If \p LR has a live value at \p Kill, prune its live range by removing
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/// any liveness reachable from Kill. Add live range end points to
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/// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
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/// value's live range.
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@ -200,8 +197,8 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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return AA;
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}
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/// isNotInMIMap - returns true if the specified machine instr has been
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/// removed or was never entered in the map.
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/// Returns true if the specified machine instr has been removed or was
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/// never entered in the map.
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bool isNotInMIMap(const MachineInstr &Instr) const {
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return !Indexes->hasIndex(Instr);
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}
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@ -270,35 +267,32 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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void releaseMemory() override;
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/// runOnMachineFunction - pass entry point
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/// Pass entry point; Calculates LiveIntervals.
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bool runOnMachineFunction(MachineFunction&) override;
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/// print - Implement the dump method.
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/// Implement the dump method.
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void print(raw_ostream &O, const Module* = nullptr) const override;
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/// intervalIsInOneMBB - If LI is confined to a single basic block, return
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/// a pointer to that block. If LI is live in to or out of any block,
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/// return NULL.
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/// If LI is confined to a single basic block, return a pointer to that
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/// block. If LI is live in to or out of any block, return NULL.
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MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
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/// Returns true if VNI is killed by any PHI-def values in LI.
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/// This may conservatively return true to avoid expensive computations.
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bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
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/// addKillFlags - Add kill flags to any instruction that kills a virtual
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/// register.
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/// Add kill flags to any instruction that kills a virtual register.
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void addKillFlags(const VirtRegMap*);
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/// handleMove - call this method to notify LiveIntervals that
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/// instruction 'mi' has been moved within a basic block. This will update
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/// the live intervals for all operands of mi. Moves between basic blocks
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/// are not supported.
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/// Call this method to notify LiveIntervals that instruction \p MI has been
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/// moved within a basic block. This will update the live intervals for all
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/// operands of \p MI. Moves between basic blocks are not supported.
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///
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/// \param UpdateFlags Update live intervals for nonallocatable physregs.
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void handleMove(MachineInstr &MI, bool UpdateFlags = false);
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/// moveIntoBundle - Update intervals for operands of MI so that they
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/// begin/end on the SlotIndex for BundleStart.
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/// Update intervals for operands of \p MI so that they begin/end on the
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/// SlotIndex for \p BundleStart.
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///
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/// \param UpdateFlags Update live intervals for nonallocatable physregs.
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///
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@ -308,10 +302,9 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
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bool UpdateFlags = false);
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/// repairIntervalsInRange - Update live intervals for instructions in a
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/// range of iterators. It is intended for use after target hooks that may
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/// insert or remove instructions, and is only efficient for a small number
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/// of instructions.
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/// Update live intervals for instructions in a range of iterators. It is
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/// intended for use after target hooks that may insert or remove
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/// instructions, and is only efficient for a small number of instructions.
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///
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/// OrigRegs is a vector of registers that were originally used by the
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/// instructions in the range between the two iterators.
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@ -334,34 +327,33 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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// LiveIntervalAnalysis maintains a sorted list of instructions with
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// register mask operands.
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/// getRegMaskSlots - Returns a sorted array of slot indices of all
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/// instructions with register mask operands.
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/// Returns a sorted array of slot indices of all instructions with
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/// register mask operands.
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ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
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/// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
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/// instructions with register mask operands in the basic block numbered
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/// MBBNum.
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/// Returns a sorted array of slot indices of all instructions with register
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/// mask operands in the basic block numbered \p MBBNum.
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ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskSlots().slice(P.first, P.second);
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}
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/// getRegMaskBits() - Returns an array of register mask pointers
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/// corresponding to getRegMaskSlots().
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/// Returns an array of register mask pointers corresponding to
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/// getRegMaskSlots().
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ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
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/// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
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/// to getRegMaskSlotsInBlock(MBBNum).
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/// Returns an array of mask pointers corresponding to
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/// getRegMaskSlotsInBlock(MBBNum).
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ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskBits().slice(P.first, P.second);
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}
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/// checkRegMaskInterference - Test if LI is live across any register mask
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/// instructions, and compute a bit mask of physical registers that are not
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/// clobbered by any of them.
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/// Test if \p LI is live across any register mask instructions, and
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/// compute a bit mask of physical registers that are not clobbered by any
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/// of them.
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///
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/// Returns false if LI doesn't cross any register mask instructions. In
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/// Returns false if \p LI doesn't cross any register mask instructions. In
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/// that case, the bit vector is not filled in.
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bool checkRegMaskInterference(LiveInterval &LI,
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BitVector &UsableRegs);
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@ -377,8 +369,8 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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// track liveness per register unit to handle aliasing registers more
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// efficiently.
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/// getRegUnit - Return the live range for Unit.
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/// It will be computed if it doesn't exist.
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/// Return the live range for register unit \p Unit. It will be computed if
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/// it doesn't exist.
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LiveRange &getRegUnit(unsigned Unit) {
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LiveRange *LR = RegUnitRanges[Unit];
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if (!LR) {
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@ -390,8 +382,8 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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return *LR;
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}
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/// getCachedRegUnit - Return the live range for Unit if it has already
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/// been computed, or NULL if it hasn't been computed yet.
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/// Return the live range for register unit \p Unit if it has already been
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/// computed, or nullptr if it hasn't been computed yet.
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LiveRange *getCachedRegUnit(unsigned Unit) {
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return RegUnitRanges[Unit];
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}
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@ -400,7 +392,7 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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return RegUnitRanges[Unit];
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}
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/// removeRegUnit - Remove computed live range for Unit. Subsequent uses
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/// Remove computed live range for register unit \p Unit. Subsequent uses
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/// should rely on on-demand recomputation.
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void removeRegUnit(unsigned Unit) {
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delete RegUnitRanges[Unit];
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@ -408,12 +400,12 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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}
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/// Remove value numbers and related live segments starting at position
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/// @p Pos that are part of any liverange of physical register @p Reg or one
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/// \p Pos that are part of any liverange of physical register \p Reg or one
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/// of its subregisters.
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void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
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/// Remove value number and related live segments of @p LI and its subranges
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/// that start at position @p Pos.
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/// Remove value number and related live segments of \p LI and its subranges
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/// that start at position \p Pos.
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void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
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/// Split separate components in LiveInterval \p LI into separate intervals.
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@ -432,10 +424,10 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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/// Compute RegMaskSlots and RegMaskBits.
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void computeRegMasks();
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/// Walk the values in @p LI and check for dead values:
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/// Walk the values in \p LI and check for dead values:
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/// - Dead PHIDef values are marked as unused.
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/// - Dead operands are marked as such.
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/// - Completely dead machine instructions are added to the @p dead vector
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/// - Completely dead machine instructions are added to the \p dead vector
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/// if it is not nullptr.
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/// Returns true if any PHI value numbers have been removed which may
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/// have separated the interval into multiple connected components.
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@ -453,8 +445,8 @@ extern cl::opt<bool> UseSegmentSetForPhysRegs;
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/// Helper function for repairIntervalsInRange(), walks backwards and
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/// creates/modifies live segments in @p LR to match the operands found.
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/// Only full operands or operands with subregisters matching @p LaneMask
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/// creates/modifies live segments in \p LR to match the operands found.
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/// Only full operands or operands with subregisters matching \p LaneMask
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/// are considered.
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void repairOldRegInRange(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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@ -7,10 +7,10 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and computes live intervals for
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// each virtual and physical register.
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/// \file This file implements the LiveInterval analysis pass which is used
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/// by the Linear Scan Register allocator. This pass linearizes the
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/// basic blocks of the function in DFS order and computes live intervals for
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/// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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@ -96,16 +96,14 @@ void LiveIntervals::releaseMemory() {
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RegMaskBits.clear();
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RegMaskBlocks.clear();
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for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
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delete RegUnitRanges[i];
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for (LiveRange *LR : RegUnitRanges)
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delete LR;
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RegUnitRanges.clear();
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// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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VNInfoAllocator.Reset();
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}
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/// runOnMachineFunction - calculates LiveIntervals
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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MF = &fn;
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MRI = &MF->getRegInfo();
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@ -135,14 +133,13 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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return true;
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}
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/// print - Implement the dump method.
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void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
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OS << "********** INTERVALS **********\n";
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// Dump the regunits.
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for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
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if (LiveRange *LR = RegUnitRanges[i])
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OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
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for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)
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if (LiveRange *LR = RegUnitRanges[Unit])
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OS << PrintRegUnit(Unit, TRI) << ' ' << *LR << '\n';
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// Dump the virtregs.
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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@ -152,8 +149,8 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
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}
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OS << "RegMasks:";
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for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
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OS << ' ' << RegMaskSlots[i];
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for (SlotIndex Idx : RegMaskSlots)
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OS << ' ' << Idx;
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OS << '\n';
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printInstrs(OS);
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@ -177,8 +174,7 @@ LiveInterval* LiveIntervals::createInterval(unsigned reg) {
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}
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/// computeVirtRegInterval - Compute the live interval of a virtual register,
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/// based on defs and uses.
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/// Compute the live interval of a virtual register, based on defs and uses.
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void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
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assert(LRCalc && "LRCalc not initialized.");
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assert(LI.empty() && "Should only compute empty intervals.");
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@ -200,7 +196,7 @@ void LiveIntervals::computeRegMasks() {
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RegMaskBlocks.resize(MF->getNumBlockIDs());
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// Find all instructions with regmask operands.
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for (MachineBasicBlock &MBB : *MF) {
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for (const MachineBasicBlock &MBB : *MF) {
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std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];
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RMB.first = RegMaskSlots.size();
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@ -210,7 +206,7 @@ void LiveIntervals::computeRegMasks() {
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RegMaskBits.push_back(Mask);
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}
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for (MachineInstr &MI : MBB) {
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for (const MachineInstr &MI : MBB) {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isRegMask())
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continue;
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@ -245,9 +241,9 @@ void LiveIntervals::computeRegMasks() {
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// interference.
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//
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/// computeRegUnitInterval - Compute the live range of a register unit, based
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/// on the uses and defs of aliasing registers. The range should be empty,
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/// or contain only dead phi-defs from ABI blocks.
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/// Compute the live range of a register unit, based on the uses and defs of
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/// aliasing registers. The range should be empty, or contain only dead
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/// phi-defs from ABI blocks.
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void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
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assert(LRCalc && "LRCalc not initialized.");
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LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
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@ -257,20 +253,21 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
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// may share super-registers. That's OK because createDeadDefs() is
|
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// idempotent. It is very rare for a register unit to have multiple roots, so
|
||||
// uniquing super-registers is probably not worthwhile.
|
||||
for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
|
||||
for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
|
||||
Supers.isValid(); ++Supers) {
|
||||
if (!MRI->reg_empty(*Supers))
|
||||
LRCalc->createDeadDefs(LR, *Supers);
|
||||
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
|
||||
for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
|
||||
Super.isValid(); ++Super) {
|
||||
unsigned Reg = *Super;
|
||||
if (!MRI->reg_empty(Reg))
|
||||
LRCalc->createDeadDefs(LR, Reg);
|
||||
}
|
||||
}
|
||||
|
||||
// Now extend LR to reach all uses.
|
||||
// Ignore uses of reserved registers. We only track defs of those.
|
||||
for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
|
||||
for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
|
||||
Supers.isValid(); ++Supers) {
|
||||
unsigned Reg = *Supers;
|
||||
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
|
||||
for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
|
||||
Super.isValid(); ++Super) {
|
||||
unsigned Reg = *Super;
|
||||
if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
|
||||
LRCalc->extendToUses(LR, Reg);
|
||||
}
|
||||
@ -281,11 +278,9 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
|
||||
LR.flushSegmentSet();
|
||||
}
|
||||
|
||||
|
||||
/// computeLiveInRegUnits - Precompute the live ranges of any register units
|
||||
/// that are live-in to an ABI block somewhere. Register values can appear
|
||||
/// without a corresponding def when entering the entry block or a landing pad.
|
||||
///
|
||||
/// Precompute the live ranges of any register units that are live-in to an ABI
|
||||
/// block somewhere. Register values can appear without a corresponding def when
|
||||
/// entering the entry block or a landing pad.
|
||||
void LiveIntervals::computeLiveInRegUnits() {
|
||||
RegUnitRanges.resize(TRI->getNumRegUnits());
|
||||
DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
|
||||
@ -294,18 +289,15 @@ void LiveIntervals::computeLiveInRegUnits() {
|
||||
SmallVector<unsigned, 8> NewRanges;
|
||||
|
||||
// Check all basic blocks for live-ins.
|
||||
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
||||
MFI != MFE; ++MFI) {
|
||||
const MachineBasicBlock *MBB = &*MFI;
|
||||
|
||||
for (const MachineBasicBlock &MBB : *MF) {
|
||||
// We only care about ABI blocks: Entry + landing pads.
|
||||
if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
|
||||
if ((&MBB != &MF->front() && !MBB.isEHPad()) || MBB.livein_empty())
|
||||
continue;
|
||||
|
||||
// Create phi-defs at Begin for all live-in registers.
|
||||
SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
|
||||
DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
|
||||
for (const auto &LI : MBB->liveins()) {
|
||||
SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
|
||||
DEBUG(dbgs() << Begin << "\tBB#" << MBB.getNumber());
|
||||
for (const auto &LI : MBB.liveins()) {
|
||||
for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
|
||||
unsigned Unit = *Units;
|
||||
LiveRange *LR = RegUnitRanges[Unit];
|
||||
@ -324,16 +316,13 @@ void LiveIntervals::computeLiveInRegUnits() {
|
||||
DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
|
||||
|
||||
// Compute the 'normal' part of the ranges.
|
||||
for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
|
||||
unsigned Unit = NewRanges[i];
|
||||
for (unsigned Unit : NewRanges)
|
||||
computeRegUnitRange(*RegUnitRanges[Unit], Unit);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void createSegmentsForValues(LiveRange &LR,
|
||||
iterator_range<LiveInterval::vni_iterator> VNIs) {
|
||||
for (auto VNI : VNIs) {
|
||||
iterator_range<LiveInterval::vni_iterator> VNIs) {
|
||||
for (VNInfo *VNI : VNIs) {
|
||||
if (VNI->isUnused())
|
||||
continue;
|
||||
SlotIndex Def = VNI->def;
|
||||
@ -349,7 +338,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
|
||||
// Keep track of the PHIs that are in use.
|
||||
SmallPtrSet<VNInfo*, 8> UsedPHIs;
|
||||
// Blocks that have already been added to WorkList as live-out.
|
||||
SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
|
||||
SmallPtrSet<const MachineBasicBlock*, 16> LiveOut;
|
||||
|
||||
// Extend intervals to reach all uses in WorkList.
|
||||
while (!WorkList.empty()) {
|
||||
@ -368,7 +357,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
|
||||
!UsedPHIs.insert(VNI).second)
|
||||
continue;
|
||||
// The PHI is live, make sure the predecessors are live-out.
|
||||
for (auto &Pred : MBB->predecessors()) {
|
||||
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
|
||||
if (!LiveOut.insert(Pred).second)
|
||||
continue;
|
||||
SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
|
||||
@ -384,7 +373,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
|
||||
LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
|
||||
|
||||
// Make sure VNI is live-out from the predecessors.
|
||||
for (auto &Pred : MBB->predecessors()) {
|
||||
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
|
||||
if (!LiveOut.insert(Pred).second)
|
||||
continue;
|
||||
SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
|
||||
@ -415,22 +404,20 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
|
||||
ShrinkToUsesWorkList WorkList;
|
||||
|
||||
// Visit all instructions reading li->reg.
|
||||
for (MachineRegisterInfo::reg_instr_iterator
|
||||
I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
|
||||
I != E; ) {
|
||||
MachineInstr *UseMI = &*(I++);
|
||||
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
|
||||
unsigned Reg = li->reg;
|
||||
for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
|
||||
if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg))
|
||||
continue;
|
||||
SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
|
||||
SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
|
||||
LiveQueryResult LRQ = li->Query(Idx);
|
||||
VNInfo *VNI = LRQ.valueIn();
|
||||
if (!VNI) {
|
||||
// This shouldn't happen: readsVirtualRegister returns true, but there is
|
||||
// no live value. It is likely caused by a target getting <undef> flags
|
||||
// wrong.
|
||||
DEBUG(dbgs() << Idx << '\t' << *UseMI
|
||||
DEBUG(dbgs() << Idx << '\t' << UseMI
|
||||
<< "Warning: Instr claims to read non-existent value in "
|
||||
<< *li << '\n');
|
||||
<< *li << '\n');
|
||||
continue;
|
||||
}
|
||||
// Special case: An early-clobber tied operand reads and writes the
|
||||
@ -458,7 +445,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
|
||||
bool LiveIntervals::computeDeadValues(LiveInterval &LI,
|
||||
SmallVectorImpl<MachineInstr*> *dead) {
|
||||
bool MayHaveSplitComponents = false;
|
||||
for (auto VNI : LI.valnos) {
|
||||
for (VNInfo *VNI : LI.valnos) {
|
||||
if (VNI->isUnused())
|
||||
continue;
|
||||
SlotIndex Def = VNI->def;
|
||||
@ -548,7 +535,7 @@ void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) {
|
||||
SR.segments.swap(NewLR.segments);
|
||||
|
||||
// Remove dead PHI value numbers
|
||||
for (auto VNI : SR.valnos) {
|
||||
for (VNInfo *VNI : SR.valnos) {
|
||||
if (VNI->isUnused())
|
||||
continue;
|
||||
const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
|
||||
@ -571,8 +558,8 @@ void LiveIntervals::extendToIndices(LiveRange &LR,
|
||||
ArrayRef<SlotIndex> Undefs) {
|
||||
assert(LRCalc && "LRCalc not initialized.");
|
||||
LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
|
||||
for (unsigned i = 0, e = Indices.size(); i != e; ++i)
|
||||
LRCalc->extend(LR, Indices[i], /*PhysReg=*/0, Undefs);
|
||||
for (SlotIndex Idx : Indices)
|
||||
LRCalc->extend(LR, Idx, /*PhysReg=*/0, Undefs);
|
||||
}
|
||||
|
||||
void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
|
||||
@ -601,11 +588,9 @@ void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
|
||||
// from each successor.
|
||||
typedef df_iterator_default_set<MachineBasicBlock*,9> VisitedTy;
|
||||
VisitedTy Visited;
|
||||
for (MachineBasicBlock::succ_iterator
|
||||
SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
|
||||
SuccI != SuccE; ++SuccI) {
|
||||
for (MachineBasicBlock *Succ : KillMBB->successors()) {
|
||||
for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
|
||||
I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
|
||||
I = df_ext_begin(Succ, Visited), E = df_ext_end(Succ, Visited);
|
||||
I != E;) {
|
||||
MachineBasicBlock *MBB = *I;
|
||||
|
||||
@ -657,9 +642,9 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
|
||||
// Find the regunit intervals for the assigned register. They may overlap
|
||||
// the virtual register live range, cancelling any kills.
|
||||
RU.clear();
|
||||
for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
|
||||
++Units) {
|
||||
const LiveRange &RURange = getRegUnit(*Units);
|
||||
for (MCRegUnitIterator Unit(VRM->getPhys(Reg), TRI); Unit.isValid();
|
||||
++Unit) {
|
||||
const LiveRange &RURange = getRegUnit(*Unit);
|
||||
if (RURange.empty())
|
||||
continue;
|
||||
RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
|
||||
@ -802,9 +787,8 @@ LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
|
||||
// Conservatively return true instead of scanning huge predecessor lists.
|
||||
if (PHIMBB->pred_size() > 100)
|
||||
return true;
|
||||
for (MachineBasicBlock::const_pred_iterator
|
||||
PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
|
||||
if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
|
||||
for (const MachineBasicBlock *Pred : PHIMBB->predecessors())
|
||||
if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(Pred)))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
@ -895,7 +879,7 @@ bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
|
||||
// IntervalUpdate class.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// HMEditor is a toolkit used by handleMove to trim or extend live intervals.
|
||||
/// Toolkit used by handleMove to trim or extend live intervals.
|
||||
class LiveIntervals::HMEditor {
|
||||
private:
|
||||
LiveIntervals& LIS;
|
||||
@ -1514,8 +1498,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
|
||||
}
|
||||
}
|
||||
|
||||
for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
|
||||
unsigned Reg = OrigRegs[i];
|
||||
for (unsigned Reg : OrigRegs) {
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
||||
continue;
|
||||
|
||||
@ -1524,16 +1507,16 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
|
||||
if (!LI.hasAtLeastOneValue())
|
||||
continue;
|
||||
|
||||
for (LiveInterval::SubRange &S : LI.subranges()) {
|
||||
for (LiveInterval::SubRange &S : LI.subranges())
|
||||
repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
|
||||
}
|
||||
|
||||
repairOldRegInRange(Begin, End, endIdx, LI, Reg);
|
||||
}
|
||||
}
|
||||
|
||||
void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
|
||||
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
||||
if (LiveRange *LR = getCachedRegUnit(*Units))
|
||||
for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
|
||||
if (LiveRange *LR = getCachedRegUnit(*Unit))
|
||||
if (VNInfo *VNI = LR->getVNInfoAt(Pos))
|
||||
LR->removeValNo(VNI);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user