From a31fa801851542b536269b60a11154d8513badb0 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 3 Oct 2007 17:10:03 +0000 Subject: [PATCH] add a note llvm-svn: 42579 --- lib/Target/X86/README.txt | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt index 39c8a02e313..8d090dff3ae 100644 --- a/lib/Target/X86/README.txt +++ b/lib/Target/X86/README.txt @@ -1330,3 +1330,35 @@ Shark tells us that using %cx in the testw instruction is sub-optimal. It suggests using the 32-bit register (which is what ICC uses). //===---------------------------------------------------------------------===// + +rdar://5506677 - We compile this: + +define i32 @foo(double %x) { + %x14 = bitcast double %x to i64 ; [#uses=1] + %tmp713 = trunc i64 %x14 to i32 ; [#uses=1] + %tmp8 = and i32 %tmp713, 2147483647 ; [#uses=1] + ret i32 %tmp8 +} + +to: + +_foo: + subl $12, %esp + fldl 16(%esp) + fstpl (%esp) + movl $2147483647, %eax + andl (%esp), %eax + addl $12, %esp + #FP_REG_KILL + ret + +It would be much better to eliminate the fldl/fstpl by folding the bitcast +into the load SDNode. That would give us: + +_foo: + movl $2147483647, %eax + andl 4(%esp), %eax + ret + +//===---------------------------------------------------------------------===// +