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Teach tblgen about instruction operands that have multiple MachineInstr

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operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
This commit is contained in:
Chris Lattner 2005-11-19 07:05:57 +00:00
parent af79013023
commit a36ad00a9a
3 changed files with 29 additions and 9 deletions
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11
utils/TableGen/CodeGenInstruction.h
View File

@ -21,6 +21,7 @@
namespace llvm {
class Record;
class DagInit;
struct CodeGenInstruction {
Record *TheDef; // The actual record defining this instruction.
@ -59,10 +60,16 @@ namespace llvm {
unsigned MIOperandNo;
unsigned MINumOperands; // The number of operands.
/// MIOperandInfo - Default MI operand type. Note an operand may be made up
/// of multiple MI operands.
DagInit *MIOperandInfo;
OperandInfo(Record *R, MVT::ValueType T, const std::string &N,
const std::string &PMN, unsigned MION, unsigned MINO)
const std::string &PMN, unsigned MION, unsigned MINO,
DagInit *MIOI)
: Rec(R), Ty(T), Name(N), PrinterMethodName(PMN), MIOperandNo(MION),
MINumOperands(MINO) {}
MINumOperands(MINO), MIOperandInfo(MIOI) {}
};
/// OperandList - The list of declared operands, along with their declared

5
utils/TableGen/CodeGenTarget.cpp
View File

@ -267,12 +267,14 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
MVT::ValueType Ty;
std::string PrintMethod = "printOperand";
unsigned NumOps = 1;
DagInit *MIOpInfo;
if (Rec->isSubClassOf("RegisterClass")) {
Ty = getValueType(Rec->getValueAsDef("RegType"));
} else if (Rec->isSubClassOf("Operand")) {
Ty = getValueType(Rec->getValueAsDef("Type"));
PrintMethod = Rec->getValueAsString("PrintMethod");
NumOps = Rec->getValueAsInt("NumMIOperands");
MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
} else if (Rec->getName() == "variable_ops") {
hasVariableNumberOfOperands = true;
continue;
@ -289,7 +291,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
" has the same name as a previous operand!";
OperandList.push_back(OperandInfo(Rec, Ty, DI->getArgName(i),
PrintMethod, MIOperandNo, NumOps));
PrintMethod, MIOperandNo, NumOps,
MIOpInfo));
MIOperandNo += NumOps;
}
}

22
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -62,13 +62,21 @@ static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
return Result; // No info for variable operand instrs.
for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
Result.push_back(Inst.OperandList[i].Rec);
else {
} else {
// This might be a multiple operand thing.
// FIXME: Targets like X86 have registers in their multi-operand operands.
for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
Result.push_back(0);
// Targets like X86 have registers in their multi-operand operands.
DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
unsigned NumDefs = MIOI->getNumArgs();
for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
if (NumDefs <= j) {
Result.push_back(0);
} else {
DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
Result.push_back(Def ? Def->getDef() : 0);
}
}
}
}
return Result;
@ -124,7 +132,9 @@ void InstrInfoEmitter::run(std::ostream &OS) {
N = ++OperandListNum;
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
if (Record *RC = OperandInfo[i]) {
Record *RC = OperandInfo[i];
// FIXME: We only care about register operands for now.
if (RC && RC->isSubClassOf("RegisterClass")) {
OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
} else {
OS << "{ 0 }, ";