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https://github.com/RPCS3/llvm-mirror.git
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[x86] add RUN for target before roundss; NFC
llvm-svn: 328601
This commit is contained in:
Sanjay Patel
parent
a54a2fbeca
commit
a38015abef
@ -1,8 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1
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define float @trunc_unsigned_f32(float %x) nounwind {
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; SSE2-LABEL: trunc_unsigned_f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttss2si %xmm0, %rax
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; SSE2-NEXT: movl %eax, %eax
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2ssq %rax, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_unsigned_f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttss2si %xmm0, %rax
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@ -23,6 +32,24 @@ define float @trunc_unsigned_f32(float %x) nounwind {
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}
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define double @trunc_unsigned_f64(double %x) nounwind {
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; SSE2-LABEL: trunc_unsigned_f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE2-NEXT: movapd %xmm0, %xmm2
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; SSE2-NEXT: subsd %xmm1, %xmm2
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; SSE2-NEXT: cvttsd2si %xmm2, %rax
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; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
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; SSE2-NEXT: xorq %rax, %rcx
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; SSE2-NEXT: cvttsd2si %xmm0, %rax
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; SSE2-NEXT: ucomisd %xmm1, %xmm0
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; SSE2-NEXT: cmovaeq %rcx, %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
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; SSE2-NEXT: subpd {{.*}}(%rip), %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
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; SSE2-NEXT: addpd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_unsigned_f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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@ -61,6 +88,34 @@ define double @trunc_unsigned_f64(double %x) nounwind {
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}
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define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) nounwind {
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; SSE2-LABEL: trunc_unsigned_v4f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm0, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm0[2,3]
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; SSE2-NEXT: cvttss2si %xmm1, %rax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: movaps %xmm0, %xmm2
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; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
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; SSE2-NEXT: cvttss2si %xmm2, %rax
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; SSE2-NEXT: movd %eax, %xmm2
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; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; SSE2-NEXT: cvttss2si %xmm0, %rax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; SSE2-NEXT: cvttss2si %xmm0, %rax
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; SSE2-NEXT: movd %eax, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,65535]
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: por {{.*}}(%rip), %xmm0
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; SSE2-NEXT: psrld $16, %xmm1
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; SSE2-NEXT: por {{.*}}(%rip), %xmm1
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; SSE2-NEXT: addps {{.*}}(%rip), %xmm1
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; SSE2-NEXT: addps %xmm0, %xmm1
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_unsigned_v4f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
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@ -109,6 +164,41 @@ define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) nounwind {
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}
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define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) nounwind {
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; SSE2-LABEL: trunc_unsigned_v2f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm0, %xmm1
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; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
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; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; SSE2-NEXT: movaps %xmm1, %xmm3
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; SSE2-NEXT: subsd %xmm2, %xmm3
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; SSE2-NEXT: cvttsd2si %xmm3, %rax
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; SSE2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
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; SSE2-NEXT: xorq %rcx, %rax
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; SSE2-NEXT: cvttsd2si %xmm1, %rdx
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; SSE2-NEXT: ucomisd %xmm2, %xmm1
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; SSE2-NEXT: cmovaeq %rax, %rdx
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; SSE2-NEXT: movaps %xmm0, %xmm1
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; SSE2-NEXT: subsd %xmm2, %xmm1
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; SSE2-NEXT: cvttsd2si %xmm1, %rax
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; SSE2-NEXT: xorq %rcx, %rax
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; SSE2-NEXT: cvttsd2si %xmm0, %rcx
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; SSE2-NEXT: ucomisd %xmm2, %xmm0
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; SSE2-NEXT: cmovaeq %rax, %rcx
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; SSE2-NEXT: movq %rcx, %xmm1
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE2-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
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; SSE2-NEXT: subpd %xmm3, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
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; SSE2-NEXT: addpd %xmm1, %xmm0
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; SSE2-NEXT: movq %rdx, %xmm1
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE2-NEXT: subpd %xmm3, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
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; SSE2-NEXT: addpd %xmm1, %xmm2
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; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_unsigned_v2f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movaps %xmm0, %xmm1
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@ -173,6 +263,68 @@ define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) nounwind {
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}
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define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) nounwind {
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; SSE2-LABEL: trunc_unsigned_v4f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm3
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; SSE2-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
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; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; SSE2-NEXT: movaps %xmm3, %xmm4
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; SSE2-NEXT: subsd %xmm2, %xmm4
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; SSE2-NEXT: cvttsd2si %xmm4, %rcx
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; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
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; SSE2-NEXT: xorq %rdx, %rcx
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; SSE2-NEXT: cvttsd2si %xmm3, %rax
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; SSE2-NEXT: ucomisd %xmm2, %xmm3
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; SSE2-NEXT: cmovaeq %rcx, %rax
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; SSE2-NEXT: movaps %xmm1, %xmm3
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; SSE2-NEXT: subsd %xmm2, %xmm3
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; SSE2-NEXT: cvttsd2si %xmm3, %rsi
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; SSE2-NEXT: xorq %rdx, %rsi
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; SSE2-NEXT: cvttsd2si %xmm1, %rcx
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; SSE2-NEXT: ucomisd %xmm2, %xmm1
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; SSE2-NEXT: cmovaeq %rsi, %rcx
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; SSE2-NEXT: movaps %xmm0, %xmm1
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; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
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; SSE2-NEXT: movaps %xmm1, %xmm3
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; SSE2-NEXT: subsd %xmm2, %xmm3
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; SSE2-NEXT: cvttsd2si %xmm3, %rsi
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; SSE2-NEXT: xorq %rdx, %rsi
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; SSE2-NEXT: cvttsd2si %xmm1, %rdi
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; SSE2-NEXT: ucomisd %xmm2, %xmm1
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; SSE2-NEXT: cmovaeq %rsi, %rdi
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; SSE2-NEXT: movaps %xmm0, %xmm1
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; SSE2-NEXT: subsd %xmm2, %xmm1
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; SSE2-NEXT: cvttsd2si %xmm1, %rsi
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; SSE2-NEXT: xorq %rdx, %rsi
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; SSE2-NEXT: cvttsd2si %xmm0, %rdx
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; SSE2-NEXT: ucomisd %xmm2, %xmm0
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; SSE2-NEXT: cmovaeq %rsi, %rdx
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; SSE2-NEXT: movq %rdx, %xmm1
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1127219200,1160773632,0,0]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE2-NEXT: movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
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; SSE2-NEXT: subpd %xmm3, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
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; SSE2-NEXT: addpd %xmm1, %xmm0
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; SSE2-NEXT: movq %rdi, %xmm1
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; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE2-NEXT: subpd %xmm3, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
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; SSE2-NEXT: addpd %xmm1, %xmm4
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; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm4[0]
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; SSE2-NEXT: movq %rcx, %xmm4
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; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
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; SSE2-NEXT: subpd %xmm3, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[2,3,0,1]
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; SSE2-NEXT: addpd %xmm4, %xmm1
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; SSE2-NEXT: movq %rax, %xmm4
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; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
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; SSE2-NEXT: subpd %xmm3, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,0,1]
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; SSE2-NEXT: addpd %xmm4, %xmm2
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; SSE2-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_unsigned_v4f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movaps %xmm1, %xmm3
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@ -282,6 +434,13 @@ define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) nounwind {
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}
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define float @trunc_signed_f32(float %x) nounwind {
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; SSE2-LABEL: trunc_signed_f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttss2si %xmm0, %eax
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2ssl %eax, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_signed_f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttss2si %xmm0, %eax
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@ -300,6 +459,13 @@ define float @trunc_signed_f32(float %x) nounwind {
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}
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define double @trunc_signed_f64(double %x) nounwind {
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; SSE2-LABEL: trunc_signed_f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttsd2si %xmm0, %rax
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2sdq %rax, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_signed_f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttsd2si %xmm0, %rax
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@ -318,6 +484,12 @@ define double @trunc_signed_f64(double %x) nounwind {
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}
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define <4 x float> @trunc_signed_v4f32(<4 x float> %x) nounwind {
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; SSE2-LABEL: trunc_signed_v4f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttps2dq %xmm0, %xmm0
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; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_signed_v4f32:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttps2dq %xmm0, %xmm0
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@ -335,6 +507,17 @@ define <4 x float> @trunc_signed_v4f32(<4 x float> %x) nounwind {
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}
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define <2 x double> @trunc_signed_v2f64(<2 x double> %x) nounwind {
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; SSE2-LABEL: trunc_signed_v2f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttsd2si %xmm0, %rax
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; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE2-NEXT: cvttsd2si %xmm0, %rcx
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2sdq %rax, %xmm0
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; SSE2-NEXT: cvtsi2sdq %rcx, %xmm1
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; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_signed_v2f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttsd2si %xmm0, %rax
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@ -361,6 +544,25 @@ define <2 x double> @trunc_signed_v2f64(<2 x double> %x) nounwind {
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}
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define <4 x double> @trunc_signed_v4f64(<4 x double> %x) nounwind {
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; SSE2-LABEL: trunc_signed_v4f64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cvttsd2si %xmm1, %rax
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; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
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; SSE2-NEXT: cvttsd2si %xmm1, %rcx
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; SSE2-NEXT: cvttsd2si %xmm0, %rdx
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; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE2-NEXT: cvttsd2si %xmm0, %rsi
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: cvtsi2sdq %rdx, %xmm0
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; SSE2-NEXT: xorps %xmm1, %xmm1
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; SSE2-NEXT: cvtsi2sdq %rsi, %xmm1
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; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: xorps %xmm1, %xmm1
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; SSE2-NEXT: cvtsi2sdq %rax, %xmm1
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; SSE2-NEXT: cvtsi2sdq %rcx, %xmm2
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; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: trunc_signed_v4f64:
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; SSE41: # %bb.0:
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; SSE41-NEXT: cvttsd2si %xmm1, %rax
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