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[SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN

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The big/small ordering here is based on signed values so SmallValue will
be INT_MIN and BigValue 0. This shouldn't be a problem but the code
assumed that BigValue always had more bits set than SmallValue.

We used to just miss the transformation, but a recent refactoring of
mine turned this into an assertion failure.

llvm-svn: 239105
This commit is contained in:
Benjamin Kramer 2015-06-04 22:05:51 +00:00
parent e029c44431
commit a384ed2381
2 changed files with 25 additions and 10 deletions
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14
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -7807,21 +7807,17 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
const APInt &BigValue = Big.Low->getValue();
// Check that there is only one bit different.
if ((BigValue ^ SmallValue).isPowerOf2()) {
// Isolate the common bit.
APInt CommonBit = BigValue & ~SmallValue;
assert((SmallValue | CommonBit) == BigValue &&
CommonBit.countPopulation() == 1 && "Not a common bit?");
APInt CommonBit = BigValue ^ SmallValue;
if (CommonBit.isPowerOf2()) {
SDValue CondLHS = getValue(Cond);
EVT VT = CondLHS.getValueType();
SDLoc DL = getCurSDLoc();
SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
DAG.getConstant(CommonBit, DL, VT));
SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
DAG.getConstant(BigValue, DL, VT),
ISD::SETEQ);
SDValue Cond = DAG.getSetCC(
DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
ISD::SETEQ);
// Update successor info.
// Both Small and Big will jump to Small.BB, so we sum up the weights.

21
test/CodeGen/X86/switch-or.ll
View File

@ -1,10 +1,11 @@
; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s
; Check that merging switch cases that differ in one bit works.
; CHECK-LABEL: test1
; CHECK: orl $2
; CHECK-NEXT: cmpl $6
define void @foo(i32 %variable) nounwind {
define void @test1(i32 %variable) nounwind {
entry:
switch i32 %variable, label %if.end [
i32 4, label %if.then
@ -19,4 +20,22 @@ if.end:
ret void
}
; CHECK-LABEL: test2
; CHECK: orl $-2147483648
; CHECK-NEXT: cmpl $-2147483648
define void @test2(i32 %variable) nounwind {
entry:
switch i32 %variable, label %if.end [
i32 0, label %if.then
i32 -2147483648, label %if.then
]
if.then:
%call = tail call i32 (...) @bar() nounwind
ret void
if.end:
ret void
}
declare i32 @bar(...) nounwind