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[AVX512] Two new attributes in X86VectorVTInfo for subvector insert

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The new attributes are NumElts and the CD8TupleForm.  This prepares the code
to enable x8 and x2 inserts.

NFC, no change in X86.td.expanded except for the new attributes.

llvm-svn: 219871
This commit is contained in:
Adam Nemet 2014-10-15 23:42:09 +00:00
parent ea53faaf7d
commit a3b1e47840
2 changed files with 14 additions and 4 deletions
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17
lib/Target/X86/X86InstrAVX512.td
View File

@ -2,9 +2,10 @@
// EltVT). These are things like the register class for the writemask, etc. // EltVT). These are things like the register class for the writemask, etc.
// The idea is to pass one of these as the template argument rather than the // The idea is to pass one of these as the template argument rather than the
// individual arguments. // individual arguments.
class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc, class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
string suffix = ""> { string suffix = ""> {
RegisterClass RC = rc; RegisterClass RC = rc;
int NumElts = numelts;
// Corresponding mask register class. // Corresponding mask register class.
RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts); RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
@ -73,6 +74,11 @@ class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
// The string to specify embedded broadcast in assembly. // The string to specify embedded broadcast in assembly.
string BroadcastStr = "{1to" # NumElts # "}"; string BroadcastStr = "{1to" # NumElts # "}";
// 8-bit compressed displacement tuple/subvector format. This is only
// defined for NumElts <= 8.
CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
!cast<CD8VForm>("CD8VT" # NumElts), ?);
SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
!if (!eq (Size, 256), sub_ymm, ?)); !if (!eq (Size, 256), sub_ymm, ?));
@ -349,7 +355,8 @@ multiclass vinsert_for_size<int Opcode,
let hasSideEffects = 0, ExeDomain = To.ExeDomain in { let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst), def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
(ins VR512:$src1, From.RC:$src2, i8imm:$src3), (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
"vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|" "vinsert" # From.EltTypeName # "x" # From.NumElts #
"\t{$src3, $src2, $src1, $dst|"
"$dst, $src1, $src2, $src3}", "$dst, $src1, $src2, $src3}",
[(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1), [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
(From.VT From.RC:$src2), (From.VT From.RC:$src2),
@ -359,9 +366,11 @@ multiclass vinsert_for_size<int Opcode,
let mayLoad = 1 in let mayLoad = 1 in
def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst), def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
(ins VR512:$src1, From.MemOp:$src2, i8imm:$src3), (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
"vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|" "vinsert" # From.EltTypeName # "x" # From.NumElts #
"\t{$src3, $src2, $src1, $dst|"
"$dst, $src1, $src2, $src3}", "$dst, $src1, $src2, $src3}",
[]>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>; []>,
EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
} }
// Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for

1
lib/Target/X86/X86InstrFormats.td
View File

@ -101,6 +101,7 @@ def CD8VF : CD8VForm<0>; // v := VL
def CD8VH : CD8VForm<1>; // v := VL/2 def CD8VH : CD8VForm<1>; // v := VL/2
def CD8VQ : CD8VForm<2>; // v := VL/4 def CD8VQ : CD8VForm<2>; // v := VL/4
def CD8VO : CD8VForm<3>; // v := VL/8 def CD8VO : CD8VForm<3>; // v := VL/8
// The tuple (subvector) forms.
def CD8VT1 : CD8VForm<4>; // v := 1 def CD8VT1 : CD8VForm<4>; // v := 1
def CD8VT2 : CD8VForm<5>; // v := 2 def CD8VT2 : CD8VForm<5>; // v := 2
def CD8VT4 : CD8VForm<6>; // v := 4 def CD8VT4 : CD8VForm<6>; // v := 4