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[Sparc] Add long double (f128) instructions to sparc backend.
llvm-svn: 189198
This commit is contained in:
Venkatraman Govindaraju
parent
1d08468931
commit
a3fc2b00cc
@ -30,6 +30,10 @@ def FeatureVIS
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: SubtargetFeature<"vis", "IsVIS", "true",
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"Enable UltraSPARC Visual Instruction Set extensions">;
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def FeatureHardQuad
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@ -1257,15 +1257,21 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
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addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
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addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
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addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
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if (Subtarget->is64Bit())
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addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
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// Turn FP extload into load/fextend
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
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// Sparc doesn't have i1 sign extending load
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// Turn FP truncstore into trunc + store.
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::f128, MVT::f32, Expand);
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setTruncStoreAction(MVT::f128, MVT::f64, Expand);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
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@ -1299,9 +1305,12 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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setOperationAction(ISD::SELECT, MVT::f128, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::f128, Expand);
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// Sparc doesn't have BRCOND either, it has BR_CC.
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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@ -1310,10 +1319,12 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::BR_CC, MVT::f128, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::BITCAST, MVT::f64, Expand);
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@ -1334,6 +1345,11 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FABS, MVT::f64, Custom);
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}
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setOperationAction(ISD::FSIN , MVT::f128, Expand);
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setOperationAction(ISD::FCOS , MVT::f128, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
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setOperationAction(ISD::FREM , MVT::f128, Expand);
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setOperationAction(ISD::FMA , MVT::f128, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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@ -1352,8 +1368,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f128, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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@ -1387,6 +1405,31 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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if (Subtarget->isV9())
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
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setOperationAction(ISD::LOAD, MVT::f128, Legal);
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setOperationAction(ISD::STORE, MVT::f128, Legal);
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} else {
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setOperationAction(ISD::LOAD, MVT::f128, Custom);
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setOperationAction(ISD::STORE, MVT::f128, Custom);
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}
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if (Subtarget->hasHardQuad()) {
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setOperationAction(ISD::FADD, MVT::f128, Legal);
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setOperationAction(ISD::FSUB, MVT::f128, Legal);
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setOperationAction(ISD::FMUL, MVT::f128, Legal);
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setOperationAction(ISD::FDIV, MVT::f128, Legal);
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setOperationAction(ISD::FSQRT, MVT::f128, Legal);
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setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
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setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
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if (Subtarget->isV9()) {
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setOperationAction(ISD::FNEG, MVT::f128, Legal);
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setOperationAction(ISD::FABS, MVT::f128, Legal);
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} else {
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setOperationAction(ISD::FNEG, MVT::f128, Custom);
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setOperationAction(ISD::FABS, MVT::f128, Custom);
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}
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}
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setMinFunctionAlignment(2);
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computeRegisterProperties();
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@ -1800,6 +1843,94 @@ static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG)
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return DstReg64;
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}
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// Lower a f128 load into two f64 loads.
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static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
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{
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SDLoc dl(Op);
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LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
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assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
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&& "Unexpected node type");
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SDValue Hi64 = DAG.getLoad(MVT::f64,
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dl,
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LdNode->getChain(),
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LdNode->getBasePtr(),
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LdNode->getPointerInfo(),
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false, false, false, 8);
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EVT addrVT = LdNode->getBasePtr().getValueType();
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SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
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LdNode->getBasePtr(),
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DAG.getConstant(8, addrVT));
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SDValue Lo64 = DAG.getLoad(MVT::f64,
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dl,
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LdNode->getChain(),
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LoPtr,
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LdNode->getPointerInfo(),
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false, false, false, 8);
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SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
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SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
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SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, MVT::f128);
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InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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MVT::f128,
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SDValue(InFP128, 0),
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Hi64,
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SubRegEven);
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InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
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MVT::f128,
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SDValue(InFP128, 0),
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Lo64,
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SubRegOdd);
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SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
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SDValue(Lo64.getNode(), 1) };
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SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&OutChains[0], 2);
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SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
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return DAG.getMergeValues(Ops, 2, dl);
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}
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// Lower a f128 store into two f64 stores.
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static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
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SDLoc dl(Op);
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StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
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assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
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&& "Unexpected node type");
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SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
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SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
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SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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dl,
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MVT::f64,
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StNode->getValue(),
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SubRegEven);
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SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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dl,
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MVT::f64,
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StNode->getValue(),
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SubRegOdd);
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SDValue OutChains[2];
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OutChains[0] = DAG.getStore(StNode->getChain(),
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dl,
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SDValue(Hi64, 0),
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StNode->getBasePtr(),
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MachinePointerInfo(),
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false, false, 8);
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EVT addrVT = StNode->getBasePtr().getValueType();
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SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
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StNode->getBasePtr(),
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DAG.getConstant(8, addrVT));
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OutChains[1] = DAG.getStore(StNode->getChain(),
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dl,
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SDValue(Lo64, 0),
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LoPtr,
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MachinePointerInfo(),
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false, false, 8);
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&OutChains[0], 2);
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}
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SDValue SparcTargetLowering::
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LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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@ -1822,6 +1953,9 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::LOAD: return LowerF128Load(Op, DAG);
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case ISD::STORE: return LowerF128Store(Op, DAG);
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}
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}
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@ -39,6 +39,10 @@ def HasNoV9 : Predicate<"!Subtarget.isV9()">;
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// HasVIS - This is true when the target processor has VIS extensions.
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def HasVIS : Predicate<"Subtarget.isVIS()">;
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// HasHardQuad - This is true when the target processor supports quad floating
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// point instructions.
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def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
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// UseDeprecatedInsts - This predicate is true when the target processor is a
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// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
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// to use when appropriate. In either of these cases, the instruction selector
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@ -354,6 +358,16 @@ def LDDFri : F3_2<3, 0b100011,
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(outs DFPRegs:$dst), (ins MEMri:$addr),
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"ldd [$addr], $dst",
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[(set f64:$dst, (load ADDRri:$addr))]>;
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def LDQFrr : F3_1<3, 0b100010,
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(outs QFPRegs:$dst), (ins MEMrr:$addr),
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"ldq [$addr], $dst",
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[(set f128:$dst, (load ADDRrr:$addr))]>,
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Requires<[HasV9, HasHardQuad]>;
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def LDQFri : F3_2<3, 0b100010,
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(outs QFPRegs:$dst), (ins MEMri:$addr),
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"ldq [$addr], $dst",
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[(set f128:$dst, (load ADDRri:$addr))]>,
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Requires<[HasV9, HasHardQuad]>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrr : F3_1<3, 0b000101,
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@ -398,6 +412,16 @@ def STDFri : F3_2<3, 0b100111,
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(outs), (ins MEMri:$addr, DFPRegs:$src),
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"std $src, [$addr]",
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[(store f64:$src, ADDRri:$addr)]>;
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def STQFrr : F3_1<3, 0b100110,
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(outs), (ins MEMrr:$addr, QFPRegs:$src),
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"stq $src, [$addr]",
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[(store f128:$src, ADDRrr:$addr)]>,
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Requires<[HasV9, HasHardQuad]>;
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def STQFri : F3_2<3, 0b100110,
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(outs), (ins MEMri:$addr, QFPRegs:$src),
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"stq $src, [$addr]",
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[(store f128:$src, ADDRri:$addr)]>,
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Requires<[HasV9, HasHardQuad]>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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@ -599,6 +623,11 @@ def FITOD : F3_3<2, 0b110100, 0b011001000,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fitod $src, $dst",
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[(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
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def FITOQ : F3_3<2, 0b110100, 0b011001100,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fitoq $src, $dst",
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[(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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// Convert Floating-point to Integer Instructions, p. 142
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def FSTOI : F3_3<2, 0b110100, 0b011010001,
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@ -609,16 +638,41 @@ def FDTOI : F3_3<2, 0b110100, 0b011010010,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
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def FQTOI : F3_3<2, 0b110100, 0b011010011,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtoi $src, $dst",
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[(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fstod $src, $dst",
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[(set f64:$dst, (fextend f32:$src))]>;
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def FSTOQ : F3_3<2, 0b110100, 0b011001101,
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(outs QFPRegs:$dst), (ins FPRegs:$src),
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"fstoq $src, $dst",
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[(set f128:$dst, (fextend f32:$src))]>,
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Requires<[HasHardQuad]>;
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def FDTOS : F3_3<2, 0b110100, 0b011000110,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtos $src, $dst",
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[(set f32:$dst, (fround f64:$src))]>;
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def FDTOQ : F3_3<2, 0b110100, 0b01101110,
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(outs QFPRegs:$dst), (ins DFPRegs:$src),
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"fdtoq $src, $dst",
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[(set f128:$dst, (fextend f64:$src))]>,
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Requires<[HasHardQuad]>;
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def FQTOS : F3_3<2, 0b110100, 0b011000111,
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(outs FPRegs:$dst), (ins QFPRegs:$src),
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"fqtos $src, $dst",
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[(set f32:$dst, (fround f128:$src))]>,
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Requires<[HasHardQuad]>;
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def FQTOD : F3_3<2, 0b110100, 0b011001011,
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(outs DFPRegs:$dst), (ins QFPRegs:$src),
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"fqtod $src, $dst",
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[(set f64:$dst, (fround f128:$src))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001,
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@ -643,6 +697,11 @@ def FSQRTD : F3_3<2, 0b110100, 0b000101010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fsqrtd $src, $dst",
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[(set f64:$dst, (fsqrt f64:$src))]>;
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def FSQRTQ : F3_3<2, 0b110100, 0b000101011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src),
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"fsqrtq $src, $dst",
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[(set f128:$dst, (fsqrt f128:$src))]>,
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Requires<[HasHardQuad]>;
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@ -655,6 +714,12 @@ def FADDD : F3_3<2, 0b110100, 0b001000010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"faddd $src1, $src2, $dst",
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[(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
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def FADDQ : F3_3<2, 0b110100, 0b001000011,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"faddq $src1, $src2, $dst",
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[(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
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Requires<[HasHardQuad]>;
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def FSUBS : F3_3<2, 0b110100, 0b001000101,
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(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
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"fsubs $src1, $src2, $dst",
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@ -663,6 +728,12 @@ def FSUBD : F3_3<2, 0b110100, 0b001000110,
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(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
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"fsubd $src1, $src2, $dst",
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[(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
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def FSUBQ : F3_3<2, 0b110100, 0b001000111,
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(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
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"fsubq $src1, $src2, $dst",
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[(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
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Requires<[HasHardQuad]>;
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// Floating-point Multiply and Divide Instructions, p. 147
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def FMULS : F3_3<2, 0b110100, 0b001001001,
|
||||
@ -673,11 +744,24 @@ def FMULD : F3_3<2, 0b110100, 0b001001010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fmuld $src1, $src2, $dst",
|
||||
[(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
|
||||
def FMULQ : F3_3<2, 0b110100, 0b001001011,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
|
||||
"fmulq $src1, $src2, $dst",
|
||||
[(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
|
||||
def FSMULD : F3_3<2, 0b110100, 0b001101001,
|
||||
(outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fsmuld $src1, $src2, $dst",
|
||||
[(set f64:$dst, (fmul (fextend f32:$src1),
|
||||
(fextend f32:$src2)))]>;
|
||||
def FDMULQ : F3_3<2, 0b110100, 0b001101110,
|
||||
(outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fdmulq $src1, $src2, $dst",
|
||||
[(set f128:$dst, (fmul (fextend f64:$src1),
|
||||
(fextend f64:$src2)))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
|
||||
def FDIVS : F3_3<2, 0b110100, 0b001001101,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fdivs $src1, $src2, $dst",
|
||||
@ -686,6 +770,11 @@ def FDIVD : F3_3<2, 0b110100, 0b001001110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fdivd $src1, $src2, $dst",
|
||||
[(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
|
||||
def FDIVQ : F3_3<2, 0b110100, 0b001001111,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
|
||||
"fdivq $src1, $src2, $dst",
|
||||
[(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
|
||||
// Floating-point Compare Instructions, p. 148
|
||||
// Note: the 2nd template arg is different for these guys.
|
||||
@ -701,6 +790,11 @@ let Defs = [FCC] in {
|
||||
(outs), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fcmpd $src1, $src2\n\tnop",
|
||||
[(SPcmpfcc f64:$src1, f64:$src2)]>;
|
||||
def FCMPQ : F3_3<2, 0b110101, 0b001010011,
|
||||
(outs), (ins QFPRegs:$src1, QFPRegs:$src2),
|
||||
"fcmpq $src1, $src2\n\tnop",
|
||||
[(SPcmpfcc f128:$src1, f128:$src2)]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -762,14 +856,28 @@ let Predicates = [HasV9] in {
|
||||
def FMOVD : F3_3<2, 0b110100, 0b000000010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fmovd $src, $dst", []>;
|
||||
def FMOVQ : F3_3<2, 0b110100, 0b000000011,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src),
|
||||
"fmovq $src, $dst", []>,
|
||||
Requires<[HasHardQuad]>;
|
||||
def FNEGD : F3_3<2, 0b110100, 0b000000110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fnegd $src, $dst",
|
||||
[(set f64:$dst, (fneg f64:$src))]>;
|
||||
def FNEGQ : F3_3<2, 0b110100, 0b000000111,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src),
|
||||
"fnegq $src, $dst",
|
||||
[(set f128:$dst, (fneg f128:$src))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
def FABSD : F3_3<2, 0b110100, 0b000001010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fabsd $src, $dst",
|
||||
[(set f64:$dst, (fabs f64:$src))]>;
|
||||
def FABSQ : F3_3<2, 0b110100, 0b000001011,
|
||||
(outs QFPRegs:$dst), (ins QFPRegs:$src),
|
||||
"fabsq $src, $dst",
|
||||
[(set f128:$dst, (fabs f128:$src))]>,
|
||||
Requires<[HasHardQuad]>;
|
||||
}
|
||||
|
||||
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
|
||||
|
||||
@ -30,7 +30,8 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
|
||||
IsV9(false),
|
||||
V8DeprecatedInsts(false),
|
||||
IsVIS(false),
|
||||
Is64Bit(is64Bit) {
|
||||
Is64Bit(is64Bit),
|
||||
HasHardQuad(false) {
|
||||
|
||||
// Determine default and user specified characteristics
|
||||
std::string CPUName = CPU;
|
||||
|
||||
@ -29,6 +29,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
|
||||
bool V8DeprecatedInsts;
|
||||
bool IsVIS;
|
||||
bool Is64Bit;
|
||||
bool HasHardQuad;
|
||||
|
||||
public:
|
||||
SparcSubtarget(const std::string &TT, const std::string &CPU,
|
||||
@ -37,6 +38,7 @@ public:
|
||||
bool isV9() const { return IsV9; }
|
||||
bool isVIS() const { return IsVIS; }
|
||||
bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
|
||||
bool hasHardQuad() const { return HasHardQuad; }
|
||||
|
||||
/// ParseSubtargetFeatures - Parses features string setting specified
|
||||
/// subtarget options. Definition of function is auto generated by tblgen.
|
||||
|
||||
27
test/CodeGen/SPARC/fp128.ll
Normal file
27
test/CodeGen/SPARC/fp128.ll
Normal file
@ -0,0 +1,27 @@
|
||||
; RUN: llc < %s -march=sparc -mattr=hard-quad-float | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: f128_ops
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: ldd
|
||||
; CHECK: faddq [[R0:.+]], [[R1:.+]], [[R2:.+]]
|
||||
; CHECK: fsubq [[R2]], [[R3:.+]], [[R4:.+]]
|
||||
; CHECK: fmulq [[R4]], [[R5:.+]], [[R6:.+]]
|
||||
; CHECK: fdivq [[R6]], [[R2]]
|
||||
; CHECK: std
|
||||
; CHECK: std
|
||||
|
||||
define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval %a, fp128* byval %b, fp128* byval %c, fp128* byval %d) {
|
||||
entry:
|
||||
%0 = load fp128* %a, align 8
|
||||
%1 = load fp128* %b, align 8
|
||||
%2 = load fp128* %c, align 8
|
||||
%3 = load fp128* %d, align 8
|
||||
%4 = fadd fp128 %0, %1
|
||||
%5 = fsub fp128 %4, %2
|
||||
%6 = fmul fp128 %5, %3
|
||||
%7 = fdiv fp128 %6, %4
|
||||
store fp128 %7, fp128* %scalar.result, align 8
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user