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[TargetLowering] Teach TargetLowering::SimplifySetCC to simplify setcc of vXi1 vectors into logic ops.
This transform was already being done for setcc of scalar i1. This extends it to vectors. llvm-svn: 323585
This commit is contained in:
Craig Topper
parent
19d11942d9
commit
a3fd6ab05d
@ -2282,50 +2282,52 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// Fold away ALL boolean setcc's.
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SDValue Temp;
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if (N0.getValueType() == MVT::i1 && foldBooleans) {
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if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
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EVT OpVT = N0.getValueType();
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switch (Cond) {
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default: llvm_unreachable("Unknown integer setcc!");
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case ISD::SETEQ: // X == Y -> ~(X^Y)
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Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
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N0 = DAG.getNOT(dl, Temp, MVT::i1);
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Temp = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
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N0 = DAG.getNOT(dl, Temp, OpVT);
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(Temp.getNode());
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break;
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case ISD::SETNE: // X != Y --> (X^Y)
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N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
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N0 = DAG.getNode(ISD::XOR, dl, OpVT, N0, N1);
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break;
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case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
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case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
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Temp = DAG.getNOT(dl, N0, MVT::i1);
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N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
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Temp = DAG.getNOT(dl, N0, OpVT);
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N0 = DAG.getNode(ISD::AND, dl, OpVT, N1, Temp);
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(Temp.getNode());
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break;
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case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
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case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
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Temp = DAG.getNOT(dl, N1, MVT::i1);
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N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
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Temp = DAG.getNOT(dl, N1, OpVT);
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N0 = DAG.getNode(ISD::AND, dl, OpVT, N0, Temp);
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(Temp.getNode());
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break;
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case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
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case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
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Temp = DAG.getNOT(dl, N0, MVT::i1);
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N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
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Temp = DAG.getNOT(dl, N0, OpVT);
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N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(Temp.getNode());
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break;
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case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
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case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
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Temp = DAG.getNOT(dl, N1, MVT::i1);
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N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
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Temp = DAG.getNOT(dl, N1, OpVT);
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N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
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break;
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}
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if (VT != MVT::i1) {
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if (VT.getScalarType() != MVT::i1) {
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if (!DCI.isCalledByLegalizer())
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DCI.AddToWorklist(N0.getNode());
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// FIXME: If running after legalize, we probably can't do this.
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N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
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ISD::NodeType ExtendCode = getExtendForContent(getBooleanContents(OpVT));
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N0 = DAG.getNode(ExtendCode, dl, VT, N0);
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}
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return N0;
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}
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@ -502,9 +502,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1
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; KNL-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
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; KNL-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
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; KNL-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
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; KNL-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
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; KNL-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; KNL-NEXT: kandnw %k0, %k1, %k1
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; KNL-NEXT: vpcmpleq %zmm1, %zmm0, %k1 {%k1}
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; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
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; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; KNL-NEXT: vzeroupper
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@ -512,9 +511,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1
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;
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; SKX-LABEL: test4:
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; SKX: ## %bb.0:
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; SKX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0
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; SKX-NEXT: vpcmpgtq %ymm3, %ymm2, %k1
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; SKX-NEXT: kandnw %k0, %k1, %k0
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; SKX-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1}
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; SKX-NEXT: vpmovm2d %k0, %xmm0
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: retq
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@ -525,9 +523,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1
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; AVX512BW-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
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; AVX512BW-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
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; AVX512BW-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
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; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
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; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; AVX512BW-NEXT: kandnw %k0, %k1, %k1
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; AVX512BW-NEXT: vpcmpleq %zmm1, %zmm0, %k1 {%k1}
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; AVX512BW-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
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; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; AVX512BW-NEXT: vzeroupper
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@ -539,9 +536,8 @@ define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1
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; AVX512DQ-NEXT: ## kill: def %ymm2 killed %ymm2 def %zmm2
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; AVX512DQ-NEXT: ## kill: def %ymm1 killed %ymm1 def %zmm1
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; AVX512DQ-NEXT: ## kill: def %ymm0 killed %ymm0 def %zmm0
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; AVX512DQ-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
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; AVX512DQ-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; AVX512DQ-NEXT: kandnw %k0, %k1, %k0
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; AVX512DQ-NEXT: vpcmpleq %zmm1, %zmm0, %k0 {%k1}
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; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
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; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; AVX512DQ-NEXT: vzeroupper
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@ -560,9 +556,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1
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; KNL-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
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; KNL-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
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; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
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; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
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; KNL-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; KNL-NEXT: kandnw %k1, %k0, %k1
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; KNL-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
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; KNL-NEXT: vpcmpleq %zmm3, %zmm2, %k1 {%k1}
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; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
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; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; KNL-NEXT: vzeroupper
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@ -570,9 +565,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1
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;
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; SKX-LABEL: test5:
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; SKX: ## %bb.0:
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; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k0
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; SKX-NEXT: vpcmpgtq %xmm3, %xmm2, %k1
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; SKX-NEXT: kandnw %k1, %k0, %k0
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; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k1
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; SKX-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1}
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; SKX-NEXT: vpmovm2q %k0, %xmm0
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; SKX-NEXT: retq
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;
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@ -582,9 +576,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1
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; AVX512BW-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
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; AVX512BW-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
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; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
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; AVX512BW-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
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; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; AVX512BW-NEXT: kandnw %k1, %k0, %k1
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; AVX512BW-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
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; AVX512BW-NEXT: vpcmpleq %zmm3, %zmm2, %k1 {%k1}
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; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
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; AVX512BW-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; AVX512BW-NEXT: vzeroupper
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@ -596,9 +589,8 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1
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; AVX512DQ-NEXT: ## kill: def %xmm2 killed %xmm2 def %zmm2
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; AVX512DQ-NEXT: ## kill: def %xmm1 killed %xmm1 def %zmm1
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; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
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; AVX512DQ-NEXT: vpcmpgtq %zmm0, %zmm1, %k0
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; AVX512DQ-NEXT: vpcmpgtq %zmm3, %zmm2, %k1
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; AVX512DQ-NEXT: kandnw %k1, %k0, %k0
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; AVX512DQ-NEXT: vpcmpgtq %zmm0, %zmm1, %k1
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; AVX512DQ-NEXT: vpcmpleq %zmm3, %zmm2, %k0 {%k1}
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; AVX512DQ-NEXT: vpmovm2q %k0, %zmm0
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; AVX512DQ-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
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; AVX512DQ-NEXT: vzeroupper
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@ -7031,18 +7031,16 @@ entry:
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define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1) {
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; GENERIC-LABEL: test4:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 # sched: [3:1.00]
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; GENERIC-NEXT: vpcmpgtq %ymm3, %ymm2, %k1 # sched: [3:1.00]
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; GENERIC-NEXT: kandnw %k0, %k1, %k0 # sched: [1:1.00]
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; GENERIC-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1} # sched: [3:1.00]
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; GENERIC-NEXT: vpmovm2d %k0, %xmm0 # sched: [1:0.33]
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; GENERIC-NEXT: vzeroupper # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: test4:
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; SKX: # %bb.0:
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; SKX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 # sched: [3:1.00]
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; SKX-NEXT: vpcmpgtq %ymm3, %ymm2, %k1 # sched: [3:1.00]
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; SKX-NEXT: kandnw %k0, %k1, %k0 # sched: [1:1.00]
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; SKX-NEXT: vpcmpleq %ymm1, %ymm0, %k0 {%k1} # sched: [3:1.00]
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; SKX-NEXT: vpmovm2d %k0, %xmm0 # sched: [1:0.25]
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; SKX-NEXT: vzeroupper # sched: [4:1.00]
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; SKX-NEXT: retq # sched: [7:1.00]
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@ -7056,17 +7054,15 @@ define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1
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define <2 x i64> @vcmp_test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1) {
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; GENERIC-LABEL: vcmp_test5:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 # sched: [3:1.00]
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; GENERIC-NEXT: vpcmpgtq %xmm3, %xmm2, %k1 # sched: [3:1.00]
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; GENERIC-NEXT: kandnw %k1, %k0, %k0 # sched: [1:1.00]
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; GENERIC-NEXT: vpcmpgtq %xmm0, %xmm1, %k1 # sched: [3:1.00]
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; GENERIC-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1} # sched: [3:1.00]
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; GENERIC-NEXT: vpmovm2q %k0, %xmm0 # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: vcmp_test5:
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; SKX: # %bb.0:
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; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k0 # sched: [3:1.00]
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; SKX-NEXT: vpcmpgtq %xmm3, %xmm2, %k1 # sched: [3:1.00]
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; SKX-NEXT: kandnw %k1, %k0, %k0 # sched: [1:1.00]
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; SKX-NEXT: vpcmpgtq %xmm0, %xmm1, %k1 # sched: [3:1.00]
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; SKX-NEXT: vpcmpleq %xmm3, %xmm2, %k0 {%k1} # sched: [3:1.00]
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; SKX-NEXT: vpmovm2q %k0, %xmm0 # sched: [1:0.25]
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; SKX-NEXT: retq # sched: [7:1.00]
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%x_gt_y = icmp slt <2 x i64> %x, %y
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@ -543,7 +543,8 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
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; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: vpcmpeqb %xmm0, %xmm5, %xmm0
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; AVX1-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vpxor %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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@ -591,7 +592,8 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
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; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2-NEXT: vpcmpeqb %xmm0, %xmm4, %xmm0
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; AVX2-NEXT: vpcmpeqb %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: vpxor %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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@ -660,97 +662,98 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) {
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define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
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; AVX1-LABEL: interleaved_load_vf32_i8_stride4:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmovdqa (%rdi), %ymm10
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; AVX1-NEXT: vmovdqa 32(%rdi), %ymm13
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; AVX1-NEXT: vmovdqa (%rdi), %ymm11
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; AVX1-NEXT: vmovdqa 32(%rdi), %ymm14
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; AVX1-NEXT: vmovdqa 64(%rdi), %ymm2
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; AVX1-NEXT: vmovdqa 96(%rdi), %ymm3
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = <u,u,u,u,0,4,8,12,u,u,u,u,u,u,u,u>
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm11
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; AVX1-NEXT: vpshufb %xmm6, %xmm11, %xmm5
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm12
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; AVX1-NEXT: vpshufb %xmm6, %xmm12, %xmm5
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; AVX1-NEXT: vpshufb %xmm6, %xmm3, %xmm7
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; AVX1-NEXT: vpunpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm12
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; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm13
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; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm4
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; AVX1-NEXT: vpshufb %xmm0, %xmm2, %xmm5
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; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm7[4,5,6,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm8
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; AVX1-NEXT: vextractf128 $1, %ymm13, %xmm14
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; AVX1-NEXT: vpshufb %xmm6, %xmm14, %xmm5
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; AVX1-NEXT: vpshufb %xmm6, %xmm13, %xmm6
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm14, %xmm15
|
||||
; AVX1-NEXT: vpshufb %xmm6, %xmm15, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm6, %xmm14, %xmm6
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm10, %xmm6
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm11, %xmm6
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm10, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm0
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm5[4,5,6,7]
|
||||
; AVX1-NEXT: vblendps {{.*#+}} ymm8 = ymm0[0,1,2,3],ymm8[4,5,6,7]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm5
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = <1,5,9,13,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm12, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm13, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm2, %xmm7
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm10, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm5, %xmm11, %xmm5
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: vblendps {{.*#+}} ymm9 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,2,6,10,14,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm11, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm12, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm13, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm2, %xmm7
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm1[4,5,6,7]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm13, %xmm0
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm6, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm10, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm11, %xmm4
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm4[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: vblendps {{.*#+}} ymm10 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm12, %xmm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm13, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm15, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm0, %xmm14, %xmm0
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm2
|
||||
; AVX1-NEXT: vpshufb %xmm3, %xmm11, %xmm3
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
|
||||
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <u,u,u,u,3,7,11,15,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm11, %xmm4
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <3,7,11,15,u,u,u,u,u,u,u,u,u,u,u,u>
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm12, %xmm5
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm14, %xmm3
|
||||
; AVX1-NEXT: vpshufb %xmm1, %xmm13, %xmm1
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm6, %xmm3
|
||||
; AVX1-NEXT: vpshufb %xmm4, %xmm10, %xmm4
|
||||
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
|
||||
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
|
||||
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm9, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm2
|
||||
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpcmpeqb %xmm9, %xmm8, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm9, %xmm3
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm4
|
||||
; AVX1-NEXT: vpcmpeqb %xmm3, %xmm4, %xmm3
|
||||
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm4
|
||||
; AVX1-NEXT: vpcmpeqb %xmm4, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpeqb %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm10, %xmm3
|
||||
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpcmpeqb %xmm0, %xmm10, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vxorps %ymm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: vxorps {{.*}}(%rip), %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: interleaved_load_vf32_i8_stride4:
|
||||
@ -845,7 +848,8 @@ define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) {
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3,4,5],ymm2[6,7]
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]
|
||||
; AVX2-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpcmpeqb %ymm0, %ymm8, %ymm0
|
||||
; AVX2-NEXT: vpxor %ymm0, %ymm8, %ymm0
|
||||
; AVX2-NEXT: vpxor {{.*}}(%rip), %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512-LABEL: interleaved_load_vf32_i8_stride4:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user