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[GlobalISel] Add generic opcodes for saturating add/subtract
Summary: Add new generic MIR opcodes G_SADDSAT etc. Add support in IRTranslator for translating the saturating add/subtract intrinsics to the new opcodes. Reviewers: aemerson, dsanders, paquette, arsenm Subscribers: jvesely, wdng, nhaehnle, rovka, hiraditya, volkan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76600
This commit is contained in:
Jay Foad
parent
33cba50434
commit
a40d0145c8
@ -243,6 +243,15 @@ These each perform their respective integer arithmetic on a scalar.
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%2:_(s32) = G_ADD %0:_(s32), %1:_(s32)
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G_SADDSAT, G_UADDSAT, G_SSUBSAT, G_USUBSAT
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Signed and unsigned addition and subtraction with saturation.
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.. code-block:: none
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%2:_(s32) = G_SADDSAT %0:_(s32), %1:_(s32)
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G_SHL, G_LSHR, G_ASHR
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^^^^^^^^^^^^^^^^^^^^^
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@ -442,6 +442,18 @@ HANDLE_TARGET_OPCODE(G_UMULH)
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// the high half of the result.
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HANDLE_TARGET_OPCODE(G_SMULH)
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/// Generic saturating unsigned addition.
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HANDLE_TARGET_OPCODE(G_UADDSAT)
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/// Generic saturating signed addition.
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HANDLE_TARGET_OPCODE(G_SADDSAT)
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/// Generic saturating unsigned subtraction.
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HANDLE_TARGET_OPCODE(G_USUBSAT)
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/// Generic saturating signed subtraction.
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HANDLE_TARGET_OPCODE(G_SSUBSAT)
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/// Generic FP addition.
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HANDLE_TARGET_OPCODE(G_FADD)
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@ -469,6 +469,42 @@ def G_SMULH : GenericInstruction {
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let isCommutable = 1;
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}
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//------------------------------------------------------------------------------
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// Saturating ops
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//------------------------------------------------------------------------------
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// Generic saturating unsigned addition.
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def G_UADDSAT : GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type0:$src2);
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let hasSideEffects = 0;
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let isCommutable = 1;
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}
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// Generic saturating signed addition.
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def G_SADDSAT : GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type0:$src2);
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let hasSideEffects = 0;
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let isCommutable = 1;
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}
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// Generic saturating unsigned subtraction.
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def G_USUBSAT : GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type0:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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// Generic saturating signed subtraction.
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def G_SSUBSAT : GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type0:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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//------------------------------------------------------------------------------
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// Floating Point Unary Ops.
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//------------------------------------------------------------------------------
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@ -1424,6 +1424,14 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
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case Intrinsic::smul_with_overflow:
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return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
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case Intrinsic::uadd_sat:
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return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
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case Intrinsic::sadd_sat:
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return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
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case Intrinsic::usub_sat:
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return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
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case Intrinsic::ssub_sat:
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return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
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case Intrinsic::fmuladd: {
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const TargetMachine &TM = MF->getTarget();
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const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
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@ -959,7 +959,11 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
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case TargetOpcode::G_SMIN:
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case TargetOpcode::G_SMAX:
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case TargetOpcode::G_UMIN:
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case TargetOpcode::G_UMAX: {
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case TargetOpcode::G_UMAX:
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case TargetOpcode::G_UADDSAT:
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case TargetOpcode::G_SADDSAT:
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case TargetOpcode::G_USUBSAT:
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case TargetOpcode::G_SSUBSAT: {
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// All these are binary ops.
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assert(DstOps.size() == 1 && "Invalid Dst");
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assert(SrcOps.size() == 2 && "Invalid Srcs");
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@ -314,6 +314,18 @@
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# DEBUG-NEXT: G_SMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_UADDSAT (opcode 117): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: G_SADDSAT (opcode 118): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: G_USUBSAT (opcode 119): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: G_SSUBSAT (opcode 120): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: G_FADD (opcode {{[0-9]+}}): 1 type index, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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318
test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
Normal file
318
test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
Normal file
@ -0,0 +1,318 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -march=amdgcn -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
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define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: name: uaddsat_i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
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; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%res = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
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ret i16 %res
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}
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declare i16 @llvm.uadd.sat.i16(i16, i16)
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define i32 @uaddsat_i32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: name: uaddsat_i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY [[UADDSAT]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%res = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
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ret i32 %res
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}
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declare i32 @llvm.uadd.sat.i32(i32, i32)
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define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: name: uaddsat_i64
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
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ret i64 %res
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}
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declare i64 @llvm.uadd.sat.i64(i64, i64)
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define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK-LABEL: name: uaddsat_v2i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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ret <2 x i32> %res
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}
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declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
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define i16 @saddsat_i16(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: name: saddsat_i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
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; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%res = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
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ret i16 %res
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}
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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define i32 @saddsat_i32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: name: saddsat_i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY [[SADDSAT]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%res = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
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ret i32 %res
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}
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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define i64 @saddsat_i64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: name: saddsat_i64
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
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ret i64 %res
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}
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK-LABEL: name: saddsat_v2i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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ret <2 x i32> %res
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}
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declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
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define i16 @usubsat_i16(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: name: usubsat_i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
|
||||
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%res = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
|
||||
ret i16 %res
|
||||
}
|
||||
declare i16 @llvm.usub.sat.i16(i16, i16)
|
||||
|
||||
define i32 @usubsat_i32(i32 %lhs, i32 %rhs) {
|
||||
; CHECK-LABEL: name: usubsat_i32
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
|
||||
; CHECK: $vgpr0 = COPY [[USUBSAT]](s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%res = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
|
||||
ret i32 %res
|
||||
}
|
||||
declare i32 @llvm.usub.sat.i32(i32, i32)
|
||||
|
||||
define i64 @usubsat_i64(i64 %lhs, i64 %rhs) {
|
||||
; CHECK-LABEL: name: usubsat_i64
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
|
||||
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||
; CHECK: [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]]
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64)
|
||||
; CHECK: $vgpr0 = COPY [[UV]](s32)
|
||||
; CHECK: $vgpr1 = COPY [[UV1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
|
||||
%res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
|
||||
ret i64 %res
|
||||
}
|
||||
declare i64 @llvm.usub.sat.i64(i64, i64)
|
||||
|
||||
define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
|
||||
; CHECK-LABEL: name: usubsat_v2i32
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
|
||||
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
|
||||
; CHECK: [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>)
|
||||
; CHECK: $vgpr0 = COPY [[UV]](s32)
|
||||
; CHECK: $vgpr1 = COPY [[UV1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
|
||||
%res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
|
||||
ret <2 x i32> %res
|
||||
}
|
||||
declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)
|
||||
|
||||
define i16 @ssubsat_i16(i16 %lhs, i16 %rhs) {
|
||||
; CHECK-LABEL: name: ssubsat_i16
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[TRUNC]], [[TRUNC1]]
|
||||
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBSAT]](s16)
|
||||
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%res = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
|
||||
ret i16 %res
|
||||
}
|
||||
declare i16 @llvm.ssub.sat.i16(i16, i16)
|
||||
|
||||
define i32 @ssubsat_i32(i32 %lhs, i32 %rhs) {
|
||||
; CHECK-LABEL: name: ssubsat_i32
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[COPY]], [[COPY1]]
|
||||
; CHECK: $vgpr0 = COPY [[SSUBSAT]](s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%res = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
|
||||
ret i32 %res
|
||||
}
|
||||
declare i32 @llvm.ssub.sat.i32(i32, i32)
|
||||
|
||||
define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) {
|
||||
; CHECK-LABEL: name: ssubsat_i64
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
|
||||
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
||||
; CHECK: [[SSUBSAT:%[0-9]+]]:_(s64) = G_SSUBSAT [[MV]], [[MV1]]
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](s64)
|
||||
; CHECK: $vgpr0 = COPY [[UV]](s32)
|
||||
; CHECK: $vgpr1 = COPY [[UV1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
|
||||
%res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
|
||||
ret i64 %res
|
||||
}
|
||||
declare i64 @llvm.ssub.sat.i64(i64, i64)
|
||||
|
||||
define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
|
||||
; CHECK-LABEL: name: ssubsat_v2i32
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
||||
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
|
||||
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
|
||||
; CHECK: [[SSUBSAT:%[0-9]+]]:_(<2 x s32>) = G_SSUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](<2 x s32>)
|
||||
; CHECK: $vgpr0 = COPY [[UV]](s32)
|
||||
; CHECK: $vgpr1 = COPY [[UV1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
|
||||
%res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
|
||||
ret <2 x i32> %res
|
||||
}
|
||||
declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
|
||||
Loading…
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Reference in New Issue
Block a user