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AMDGPU/R600: Remove intrinsics with no tests and no users
Mesa removed this path, so nothing is using these anymore. llvm-svn: 275372
This commit is contained in:
Matt Arsenault
parent
cfd2c39f42
commit
a42057703b
@ -12,7 +12,8 @@
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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class AMDGPUInst <dag outs, dag ins, string asm = "",
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list<dag> pattern = []> : Instruction {
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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@ -35,11 +36,10 @@ class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instructio
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let TSFlags{62} = isRegisterStore;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
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list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
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@ -669,24 +669,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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SDLoc DL(Op);
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switch(IntrinsicID) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case AMDGPUIntrinsic::R600_interp_xy:
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case AMDGPUIntrinsic::R600_interp_zw: {
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int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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MachineSDNode *interp;
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SDValue RegisterINode = Op.getOperand(2);
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SDValue RegisterJNode = Op.getOperand(3);
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if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
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interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
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MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
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RegisterJNode, RegisterINode);
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else
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interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
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MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
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RegisterJNode, RegisterINode);
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return DAG.getBuildVector(MVT::v2f32, DL,
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{SDValue(interp, 0), SDValue(interp, 1)});
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}
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case AMDGPUIntrinsic::r600_tex:
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case AMDGPUIntrinsic::r600_texc:
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case AMDGPUIntrinsic::r600_txl:
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@ -696,8 +678,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case AMDGPUIntrinsic::r600_txf:
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case AMDGPUIntrinsic::r600_txq:
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case AMDGPUIntrinsic::r600_ddx:
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case AMDGPUIntrinsic::r600_ddy:
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case AMDGPUIntrinsic::R600_ldptr: {
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case AMDGPUIntrinsic::r600_ddy: {
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unsigned TextureOp;
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::r600_tex:
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@ -730,9 +711,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case AMDGPUIntrinsic::r600_ddy:
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TextureOp = 9;
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break;
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case AMDGPUIntrinsic::R600_ldptr:
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TextureOp = 10;
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break;
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default:
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llvm_unreachable("Unknow Texture Operation");
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}
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@ -15,7 +15,7 @@
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include "R600Intrinsics.td"
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include "R600InstrFormats.td"
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class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
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class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> :
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InstR600 <outs, ins, asm, pattern, NullALU> {
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let Namespace = "AMDGPU";
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@ -434,8 +434,7 @@ def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
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def INTERP_VEC_LOAD : AMDGPUShaderInst <
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(outs R600_Reg128:$dst),
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(ins i32imm:$src0),
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"INTERP_LOAD $src0 : $dst",
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[(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>;
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"INTERP_LOAD $src0 : $dst">;
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def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
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let bank_swizzle = 5;
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@ -501,28 +500,6 @@ class ExportBufWord1 {
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}
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multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
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def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
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(ExportInst
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
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0, 61, 0, 7, 7, 7, cf_inst, 0)
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>;
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def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
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(ExportInst
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(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
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0, 61, 7, 0, 7, 7, cf_inst, 0)
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>;
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def : Pat<(int_R600_store_dummy (i32 imm:$type)),
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(ExportInst
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(v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
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>;
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def : Pat<(int_R600_store_dummy 1),
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(ExportInst
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(v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
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>;
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
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(i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$base,
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@ -1449,8 +1426,7 @@ def TEX_VTX_CONSTBUF :
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}
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def TEX_VTX_TEXBUF:
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InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
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[(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
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InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
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VTX_WORD1_GPR, VTX_WORD0_eg {
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let VC_INST = 0;
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@ -25,6 +25,13 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
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}
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let TargetPrefix = "R600", isTarget = 1 in {
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def int_R600_store_swizzle :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_stream_output :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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} // End TargetPrefix = "R600", isTarget = 1
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let TargetPrefix = "r600", isTarget = 1 in {
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class TextureIntrinsicFloatInput :
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Intrinsic<[llvm_v4f32_ty], [
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llvm_v4f32_ty, // Coord
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@ -52,29 +59,7 @@ let TargetPrefix = "R600", isTarget = 1 in {
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llvm_i32_ty // coord_type_w
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], [IntrNoMem]>;
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def int_R600_ldptr : TextureIntrinsicInt32Input;
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def int_R600_interp_const :
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Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_R600_interp_xy :
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Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_R600_interp_zw :
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Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_R600_load_texbuf :
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Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_R600_store_swizzle :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_stream_output :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_pixel_depth :
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Intrinsic<[], [llvm_float_ty], []>;
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def int_R600_store_pixel_stencil :
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Intrinsic<[], [llvm_float_ty], []>;
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def int_R600_store_dummy :
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Intrinsic<[], [llvm_i32_ty], []>;
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} // End TargetPrefix = "R600", isTarget = 1
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let TargetPrefix = "r600", isTarget = 1 in {
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def int_r600_tex : TextureIntrinsicFloatInput;
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def int_r600_texc : TextureIntrinsicFloatInput;
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def int_r600_txl : TextureIntrinsicFloatInput;
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