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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 03:02:36 +01:00
Enable tail calls on ARM by default, with some
basic tests. This has been well tested on Darwin but not elsewhere. It should work provided the linker correctly resolves B.W <label in other function> which it has not seen before, at least from llvm-based compilers. I'm leaving the arm-tail-calls switch in until I see if there's any problems because of that; it might need to be disabled for some environments. llvm-svn: 106299
This commit is contained in:
Dale Johannesen
parent
f03db5dcc6
commit
a441c8fd45
@ -55,7 +55,7 @@ STATISTIC(NumTailCalls, "Number of tail calls");
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static cl::opt<bool>
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EnableARMTailCalls("arm-tail-calls", cl::Hidden,
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cl::desc("Generate tail calls (TEMPORARY OPTION)."),
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cl::init(false));
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cl::init(true));
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static cl::opt<bool>
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EnableARMLongCalls("arm-long-calls", cl::Hidden,
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36
test/CodeGen/ARM/call-tc.ll
Normal file
36
test/CodeGen/ARM/call-tc.ll
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@ -0,0 +1,36 @@
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; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
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; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
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; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
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; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
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@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
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declare void @g(i32, i32, i32, i32)
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define void @f() {
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; CHECKELF: PLT
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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}
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define void @g.upgrd.1() {
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; CHECKV4: bx r0 @ TAILCALL
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; CHECKV5: bx r0 @ TAILCALL
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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ret void
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}
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define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
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; CHECKV4: m_231b
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; CHECKV4: bx r{{.*}}
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BB0:
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%5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
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%t35 = volatile load i32* %5 ; <i32> [#uses=1]
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%6 = inttoptr i32 %t35 to i32** ; <i32**> [#uses=1]
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%7 = getelementptr i32** %6, i32 86 ; <i32**> [#uses=1]
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%8 = load i32** %7 ; <i32*> [#uses=1]
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%9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; <i32* (i32, i32*, i32, i32*, i32*, i32*)*> [#uses=1]
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%10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1]
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ret i32* %10
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}
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23
test/CodeGen/ARM/ifcvt6-tc.ll
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23
test/CodeGen/ARM/ifcvt6-tc.ll
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@ -0,0 +1,23 @@
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; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
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; RUN: grep cmpne | count 1
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; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
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; RUN: grep bhi | count 1
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; Here, tail call wins over eliminating branches. It is 1 fewer instruction
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; and removes all stack accesses, so seems like a win.
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define void @foo(i32 %X, i32 %Y) {
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entry:
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%tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
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%tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
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%tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
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br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
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cond_true: ; preds = %entry
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%tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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declare i32 @bar(...)
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11
test/CodeGen/ARM/insn-sched1-tc.ll
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11
test/CodeGen/ARM/insn-sched1-tc.ll
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@ -0,0 +1,11 @@
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; RUN: llc < %s -march=arm -mattr=+v6
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; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\
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; RUN: grep mov | count 2
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define i32 @test(i32 %x) {
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%tmp = trunc i32 %x to i16 ; <i16> [#uses=1]
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%tmp2 = tail call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1]
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ret i32 %tmp2
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}
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declare i32 @f(i32, i16)
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37
test/CodeGen/ARM/ldm-tc.ll
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37
test/CodeGen/ARM/ldm-tc.ll
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@ -0,0 +1,37 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
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define i32 @t1() {
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; CHECK: t1:
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; CHECK: ldmia
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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define i32 @t2() {
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; CHECK: t2:
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; CHECK: ldmia
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
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%tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @t3() {
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; CHECK: t3:
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; CHECK: ldmib
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; CHECK: b.w _f2 @ TAILCALL
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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declare i32 @f1(i32, i32)
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declare i32 @f2(i32, i32, i32)
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27
test/CodeGen/Thumb2/thumb2-call-tc.ll
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27
test/CodeGen/Thumb2/thumb2-call-tc.ll
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@ -0,0 +1,27 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN
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; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX
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@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
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declare void @g(i32, i32, i32, i32)
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define void @f() {
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; DARWIN: f:
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; DARWIN: blx _g
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; LINUX: f:
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; LINUX: bl g
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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}
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define void @h() {
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; DARWIN: h:
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; DARWIN: bx r0 @ TAILCALL
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; LINUX: h:
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; LINUX: bx r0 @ TAILCALL
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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ret void
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}
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86
test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
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86
test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
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@ -0,0 +1,86 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK: t1:
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; CHECK: it ne
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; CHECK: cmpne
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switch i32 %c, label %cond_next [
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i32 1, label %cond_true
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i32 7, label %cond_true
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]
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cond_true:
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%tmp12 = add i32 %a, 1
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%tmp1518 = add i32 %tmp12, %b
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ret i32 %tmp1518
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cond_next:
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%tmp15 = add i32 %b, %a
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ret i32 %tmp15
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}
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; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
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define i32 @t2(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: ite gt
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; CHECK: subgt
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; CHECK: suble
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%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
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br i1 %tmp1434, label %bb17, label %bb.outer
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bb.outer: ; preds = %cond_false, %entry
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%b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
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%a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %cond_true, %bb.outer
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%indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
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%tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
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%tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
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%a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
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%tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
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br i1 %tmp3, label %cond_true, label %cond_false
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cond_true: ; preds = %bb
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%tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
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%tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
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br i1 %tmp1437, label %bb17, label %bb
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cond_false: ; preds = %bb
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%tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
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%tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
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br i1 %tmp14, label %bb17, label %bb.outer
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bb17: ; preds = %cond_false, %cond_true, %entry
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%a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
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ret i32 %a_addr.026.1
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}
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@x = external global i32* ; <i32**> [#uses=1]
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define void @foo(i32 %a) nounwind {
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entry:
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%tmp = load i32** @x ; <i32*> [#uses=1]
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store i32 %a, i32* %tmp
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ret void
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}
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; Tail call prevents use of ifcvt in this one. Seems like a win though.
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define void @t3(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: t3:
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; CHECK-NOT: it lt
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; CHECK-NOT: poplt
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; CHECK: b.w _foo @ TAILCALL
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%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
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br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
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cond_true: ; preds = %entry
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tail call void @foo( i32 %b )
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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