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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
* Must save FP registers when calling CompilationCallback(), because FP
registers are global, are NOT windowed, and hence can be clobbered! * Removed unused register shorthand notations * Fixed and cleaned up comments in inline assembly llvm-svn: 7853
This commit is contained in:
Misha Brukman
parent
6b9c20230f
commit
a45f4930ed
@ -75,7 +75,8 @@ namespace {
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private:
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uint64_t emitStubForFunction(Function *F);
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static void CompilationCallback();
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static void SaveRestoreRegisters();
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static uint64_t CompilationCallback();
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uint64_t resolveFunctionReference(uint64_t RetAddr);
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};
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@ -91,7 +92,7 @@ namespace {
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///
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uint64_t JITResolver::addFunctionReference(uint64_t Address, Function *F) {
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LazyCodeGenMap[Address] = F;
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return (intptr_t)&JITResolver::CompilationCallback;
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return (intptr_t)&JITResolver::SaveRestoreRegisters;
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}
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/// deleteFunctionReference - If we are emitting a far call, we already added a
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@ -126,8 +127,7 @@ uint64_t JITResolver::getLazyResolver(Function *F) {
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uint64_t JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
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static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
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i7 = SparcIntRegClass::i7,
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static const unsigned
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o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
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g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
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@ -143,7 +143,7 @@ uint64_t JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
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BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
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// sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
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BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
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// or %g5, %g1, %g1 ;; get upper word (in %i1) into %g1
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// or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
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BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
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// or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
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BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
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@ -162,12 +162,159 @@ uint64_t JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
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return Addr;
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}
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void JITResolver::CompilationCallback() {
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uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
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void JITResolver::SaveRestoreRegisters() {
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uint32_t SingleFP[32];
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uint64_t DoubleFP[16];
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// FIXME: uint128_t QuadFloatRegs[..];
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uint64_t CCR, FSR, FPRS, g1, g5;
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#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
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__asm__ __volatile__ (// Save g1 and g5
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"stx %%g1, %0;\n\t" "stx %%g5, %1;\n\t"
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: "=m"(g1), "=m"(g5));
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__asm__ __volatile__ (// Save condition-code registers
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"stx %%fsr, %0;\n\t"
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"rd %%fprs, %1;\n\t"
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"rd %%ccr, %2;\n\t"
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: "=m"(FSR), "=r"(FPRS), "=r"(CCR));
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// GCC says: `asm' only allows up to thirty parameters!
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__asm__ __volatile__ (// Save Single FP registers, part 1
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"st %%f0, %0;\n\t" "st %%f1, %1;\n\t"
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"st %%f2, %2;\n\t" "st %%f3, %3;\n\t"
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"st %%f4, %4;\n\t" "st %%f5, %5;\n\t"
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"st %%f6, %6;\n\t" "st %%f7, %7;\n\t"
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"st %%f8, %8;\n\t" "st %%f9, %9;\n\t"
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"st %%f10, %10;\n\t" "st %%f11, %11;\n\t"
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"st %%f12, %12;\n\t" "st %%f13, %13;\n\t"
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"st %%f14, %14;\n\t" "st %%f15, %15;\n\t"
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: "=m"(SingleFP[ 0]), "=m"(SingleFP[ 1]),
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"=m"(SingleFP[ 2]), "=m"(SingleFP[ 3]),
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"=m"(SingleFP[ 4]), "=m"(SingleFP[ 5]),
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"=m"(SingleFP[ 6]), "=m"(SingleFP[ 7]),
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"=m"(SingleFP[ 8]), "=m"(SingleFP[ 9]),
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"=m"(SingleFP[10]), "=m"(SingleFP[11]),
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"=m"(SingleFP[12]), "=m"(SingleFP[13]),
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"=m"(SingleFP[14]), "=m"(SingleFP[15]));
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__asm__ __volatile__ (// Save Single FP registers, part 2
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"st %%f16, %0;\n\t" "st %%f17, %1;\n\t"
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"st %%f18, %2;\n\t" "st %%f19, %3;\n\t"
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"st %%f20, %4;\n\t" "st %%f21, %5;\n\t"
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"st %%f22, %6;\n\t" "st %%f23, %7;\n\t"
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"st %%f24, %8;\n\t" "st %%f25, %9;\n\t"
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"st %%f26, %10;\n\t" "st %%f27, %11;\n\t"
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"st %%f28, %12;\n\t" "st %%f29, %13;\n\t"
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"st %%f30, %14;\n\t" "st %%f31, %15;\n\t"
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: "=m"(SingleFP[16]), "=m"(SingleFP[17]),
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"=m"(SingleFP[18]), "=m"(SingleFP[19]),
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"=m"(SingleFP[20]), "=m"(SingleFP[21]),
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"=m"(SingleFP[22]), "=m"(SingleFP[23]),
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"=m"(SingleFP[24]), "=m"(SingleFP[25]),
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"=m"(SingleFP[26]), "=m"(SingleFP[27]),
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"=m"(SingleFP[28]), "=m"(SingleFP[29]),
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"=m"(SingleFP[30]), "=m"(SingleFP[31]));
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__asm__ __volatile__ (// Save Double FP registers
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"std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
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"std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
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"std %%f40, %4;\n\t" "std %%f42, %5;\n\t"
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"std %%f44, %6;\n\t" "std %%f46, %7;\n\t"
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"std %%f48, %8;\n\t" "std %%f50, %9;\n\t"
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"std %%f52, %10;\n\t" "std %%f54, %11;\n\t"
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"std %%f56, %12;\n\t" "std %%f58, %13;\n\t"
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"std %%f60, %14;\n\t" "std %%f62, %15;\n\t"
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: "=m"(DoubleFP[32/2-16]), "=m"(DoubleFP[34/2-16]),
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"=m"(DoubleFP[36/2-16]), "=m"(DoubleFP[38/2-16]),
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"=m"(DoubleFP[40/2-16]), "=m"(DoubleFP[42/2-16]),
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"=m"(DoubleFP[44/2-16]), "=m"(DoubleFP[46/2-16]),
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"=m"(DoubleFP[48/2-16]), "=m"(DoubleFP[50/2-16]),
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"=m"(DoubleFP[52/2-16]), "=m"(DoubleFP[54/2-16]),
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"=m"(DoubleFP[56/2-16]), "=m"(DoubleFP[58/2-16]),
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"=m"(DoubleFP[60/2-16]), "=m"(DoubleFP[62/2-16]));
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#endif
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// Resolve the function call
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register uint64_t restoreAddr = CompilationCallback();
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#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
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// Set the return address to re-execute the `restore' instruction
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__asm__ __volatile__ ("or %%o0, %%g0, %%i7;\n\t"
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// Restore g1 and g5
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"ldx %0, %%g1;\n\t" "ldx %1, %%g5;\n\t"
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:: "m"(g1), "m"(g5));
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__asm__ __volatile__ (// Restore condition-code registers
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"ldx %0, %%fsr;\n\t"
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"wr %1, 0, %%fprs;\n\t"
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"wr %2, 0, %%ccr;\n\t"
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:: "m"(FSR), "r"(FPRS), "r"(CCR));
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// GCC says: `asm' only allows up to thirty parameters!
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__asm__ __volatile__ (// Restore Single FP registers, part 1
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"ld %0, %%f0;\n\t" "ld %1, %%f1;\n\t"
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"ld %2, %%f2;\n\t" "ld %3, %%f3;\n\t"
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"ld %4, %%f4;\n\t" "ld %5, %%f5;\n\t"
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"ld %6, %%f6;\n\t" "ld %7, %%f7;\n\t"
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"ld %8, %%f8;\n\t" "ld %9, %%f9;\n\t"
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"ld %10, %%f10;\n\t" "ld %11, %%f11;\n\t"
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"ld %12, %%f12;\n\t" "ld %13, %%f13;\n\t"
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"ld %14, %%f14;\n\t" "ld %15, %%f15;\n\t"
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:: "m"(SingleFP[0]), "m"(SingleFP[1]),
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"m"(SingleFP[2]), "m"(SingleFP[3]),
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"m"(SingleFP[4]), "m"(SingleFP[5]),
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"m"(SingleFP[6]), "m"(SingleFP[7]),
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"m"(SingleFP[8]), "m"(SingleFP[9]),
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"m"(SingleFP[10]), "m"(SingleFP[11]),
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"m"(SingleFP[12]), "m"(SingleFP[13]),
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"m"(SingleFP[14]), "m"(SingleFP[15]));
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__asm__ __volatile__ (// Restore Single FP registers, part 2
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"ld %0, %%f16;\n\t" "ld %1, %%f17;\n\t"
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"ld %2, %%f18;\n\t" "ld %3, %%f19;\n\t"
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"ld %4, %%f20;\n\t" "ld %5, %%f21;\n\t"
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"ld %6, %%f22;\n\t" "ld %7, %%f23;\n\t"
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"ld %8, %%f24;\n\t" "ld %9, %%f25;\n\t"
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"ld %10, %%f26;\n\t" "ld %11, %%f27;\n\t"
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"ld %12, %%f28;\n\t" "ld %13, %%f29;\n\t"
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"ld %14, %%f30;\n\t" "ld %15, %%f31;\n\t"
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:: "m"(SingleFP[16]), "m"(SingleFP[17]),
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"m"(SingleFP[18]), "m"(SingleFP[19]),
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"m"(SingleFP[20]), "m"(SingleFP[21]),
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"m"(SingleFP[22]), "m"(SingleFP[23]),
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"m"(SingleFP[24]), "m"(SingleFP[25]),
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"m"(SingleFP[26]), "m"(SingleFP[27]),
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"m"(SingleFP[28]), "m"(SingleFP[29]),
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"m"(SingleFP[30]), "m"(SingleFP[31]));
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__asm__ __volatile__ (// Restore Double FP registers
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"ldd %0, %%f32;\n\t" "ldd %1, %%f34;\n\t"
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"ldd %2, %%f36;\n\t" "ldd %3, %%f38;\n\t"
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"ldd %4, %%f40;\n\t" "ldd %5, %%f42;\n\t"
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"ldd %6, %%f44;\n\t" "ldd %7, %%f46;\n\t"
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"ldd %8, %%f48;\n\t" "ldd %9, %%f50;\n\t"
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"ldd %10, %%f52;\n\t" "ldd %11, %%f54;\n\t"
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"ldd %12, %%f56;\n\t" "ldd %13, %%f58;\n\t"
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"ldd %14, %%f60;\n\t" "ldd %15, %%f62;\n\t"
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:: "m"(DoubleFP[32/2-16]), "m"(DoubleFP[34/2-16]),
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"m"(DoubleFP[36/2-16]), "m"(DoubleFP[38/2-16]),
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"m"(DoubleFP[40/2-16]), "m"(DoubleFP[42/2-16]),
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"m"(DoubleFP[44/2-16]), "m"(DoubleFP[46/2-16]),
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"m"(DoubleFP[48/2-16]), "m"(DoubleFP[50/2-16]),
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"m"(DoubleFP[52/2-16]), "m"(DoubleFP[54/2-16]),
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"m"(DoubleFP[56/2-16]), "m"(DoubleFP[58/2-16]),
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"m"(DoubleFP[60/2-16]), "m"(DoubleFP[62/2-16]));
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#endif
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}
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uint64_t JITResolver::CompilationCallback() {
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uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(1);
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int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
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DEBUG(std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n");
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register int64_t returnAddr = 0;
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#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
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register int64_t returnAddr;
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__asm__ __volatile__ ("add %%i7, %%g0, %0" : "=r" (returnAddr) : );
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DEBUG(std::cerr << "Read i7 (return addr) = "
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<< std::hex << returnAddr << ", value: "
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@ -181,7 +328,7 @@ void JITResolver::CompilationCallback() {
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// Subtract enough to overwrite up to the 'save' instruction
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// This depends on whether we made a short call (1 instruction) or the
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// farCall (long form: 10 instructions, short form: 7 instructions)
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// farCall (7 instructions)
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uint64_t Offset = (LazyCallFlavor[CameFrom] == ShortCall) ? 4 : 28;
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uint64_t CodeBegin = CameFrom - Offset;
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@ -210,14 +357,13 @@ void JITResolver::CompilationCallback() {
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delete MI;
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#endif
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// Change the return address to reexecute the restore, then the jump
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// The return address is really %o7, but will disappear after this function
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// returns, and the register windows are rotated away.
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#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
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__asm__ __volatile__ ("sub %%i7, %0, %%i7" : : "r" (Offset+12));
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DEBUG(std::cerr << "Callback setting return addr to "
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// Change the return address to reexecute the restore, then the jump However,
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// we can't just modify %i7 here, because we return to the function that will
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// restore the floating-point registers for us. Thus, we just return the value
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// we want it to be, and the parent will take care of setting %i7 correctly.
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DEBUG(std::cerr << "Callback returning the addr of restore inst: "
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<< std::hex << (CameFrom-Offset-12) << "\n");
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#endif
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return CameFrom - Offset - 12; // 8 because of call+delay, 4 more to restore
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}
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/// emitStubForFunction - This method is used by the JIT when it needs to emit
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@ -295,7 +441,7 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) {
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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MachineInstr &MI) {
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MachineInstr &MI) {
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const TargetRegInfo &RI = TM.getRegInfo();
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unsigned regClass, regType = RI.getRegType(fakeReg);
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// At least map fakeReg into its class
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@ -359,8 +505,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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// WARNING: if the call used the delay slot to do meaningful work, that's not
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// being accounted for, and the behavior will be incorrect!!
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inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
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static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
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i7 = SparcIntRegClass::i7, o6 = SparcIntRegClass::o6,
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static const unsigned o6 = SparcIntRegClass::o6,
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o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0,
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g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
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@ -372,17 +517,17 @@ inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
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BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
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// or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %1
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BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
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// sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
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// sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
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BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
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// sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
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BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
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// or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
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// or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
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BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
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// or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
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BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
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// jmpl %g1, %g0, %o7 ;; indirect call on %g1
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// jmpl %g1, %g0, %o7 ;; indirect call on %g1
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BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(o7),
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// nop ;; delay slot
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// nop ;; delay slot
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BuildMI(V9::NOP, 0)
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};
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@ -673,5 +818,4 @@ void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI,
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}
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}
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#include "SparcV9CodeEmitter.inc"
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