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Revert "[AArch64] Lower calls with rv_marker attribute ."
This reverts commit a87fccb3ff9c11986d3110d9f77fb0ccea0daf79. A test appears to fail with expensive checks. Reverting while I investigate.
This commit is contained in:
Florian Hahn
parent
e5edf9f654
commit
a480e97ce0
@ -83,8 +83,6 @@ private:
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bool expandSVESpillFill(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned Opc,
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unsigned N);
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bool expandCALL_RVMARKER(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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};
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} // end anonymous namespace
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@ -629,46 +627,6 @@ bool AArch64ExpandPseudo::expandSVESpillFill(MachineBasicBlock &MBB,
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return true;
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}
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bool AArch64ExpandPseudo::expandCALL_RVMARKER(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
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// Expand CALL_RVMARKER pseudo to a branch, followed by the special `mov x29,
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// x29` marker. Mark the sequence as bundle, to avoid passes moving other code
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// in between.
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MachineInstr &MI = *MBBI;
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MachineInstr *OriginalCall;
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MachineOperand &CallTarget = MI.getOperand(0);
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assert((CallTarget.isGlobal() || CallTarget.isReg()) &&
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"invalid operand for regular call");
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unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR;
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OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
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OriginalCall->addOperand(CallTarget);
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unsigned RegMaskStartIdx = 1;
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// Skip register arguments. Those are added during ISel, but are not
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// needed for the concrete branch.
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while (!MI.getOperand(RegMaskStartIdx).isRegMask()) {
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assert(MI.getOperand(RegMaskStartIdx).isReg() &&
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"should only skip register operands");
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RegMaskStartIdx++;
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}
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for (; RegMaskStartIdx < MI.getNumOperands(); ++RegMaskStartIdx)
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OriginalCall->addOperand(MI.getOperand(RegMaskStartIdx));
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auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs))
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.addReg(AArch64::FP)
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.addReg(AArch64::XZR)
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.addReg(AArch64::FP)
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.addImm(0)
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.getInstr();
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if (MI.shouldUpdateCallSiteInfo())
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MBB.getParent()->moveCallSiteInfo(&MI, Marker);
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MI.eraseFromParent();
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finalizeBundle(MBB, OriginalCall->getIterator(),
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std::next(Marker->getIterator()));
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return true;
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}
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/// If MBBI references a pseudo instruction that should be expanded here,
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/// do the expansion and return true. Otherwise return false.
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bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
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@ -1056,8 +1014,6 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
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return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 3);
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case AArch64::LDR_ZZXI:
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return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2);
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case AArch64::BLR_RVMARKER:
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return expandCALL_RVMARKER(MBB, MBBI);
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}
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return false;
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}
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@ -1934,7 +1934,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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MAKE_CASE(AArch64ISD::INDEX_VECTOR)
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MAKE_CASE(AArch64ISD::UABD)
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MAKE_CASE(AArch64ISD::SABD)
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MAKE_CASE(AArch64ISD::CALL_RVMARKER)
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}
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#undef MAKE_CASE
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return nullptr;
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@ -5540,17 +5539,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
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return Ret;
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}
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unsigned CallOpc = AArch64ISD::CALL;
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// Calls marked with "rv_marker" are special. They should be expanded to the
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// call, directly followed by a special marker sequence. Use the CALL_RVMARKER
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// to do that.
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if (CLI.CB && CLI.CB->hasRetAttr("rv_marker")) {
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assert(!IsTailCall && "tail calls cannot be marked with rv_marker");
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CallOpc = AArch64ISD::CALL_RVMARKER;
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}
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// Returns a chain and a flag for retval copy to use.
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Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops);
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Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
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DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
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InFlag = Chain.getValue(1);
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DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
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@ -417,11 +417,7 @@ enum NodeType : unsigned {
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LDP,
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STP,
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STNP,
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// Pseudo for a OBJC call that gets emitted together with a special `mov
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// x29, x29` marker instruction.
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CALL_RVMARKER
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STNP
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};
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} // end namespace AArch64ISD
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@ -399,12 +399,6 @@ def AArch64call : SDNode<"AArch64ISD::CALL",
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SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER",
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SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
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[SDNPHasChain]>;
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def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
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@ -2095,8 +2089,6 @@ let isCall = 1, Defs = [LR], Uses = [SP] in {
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def BLRNoIP : Pseudo<(outs), (ins GPR64noip:$Rn), []>,
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Sched<[WriteBrReg]>,
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PseudoInstExpansion<(BLR GPR64:$Rn)>;
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def BLR_RVMARKER : Pseudo<(outs), (ins variable_ops), []>,
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Sched<[WriteBrReg]>;
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} // isCall
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def : Pat<(AArch64call GPR64:$Rn),
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@ -2106,10 +2098,6 @@ def : Pat<(AArch64call GPR64noip:$Rn),
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(BLRNoIP GPR64noip:$Rn)>,
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Requires<[SLSBLRMitigation]>;
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def : Pat<(AArch64call_rvmarker GPR64:$Rn),
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(BLR_RVMARKER GPR64:$Rn)>,
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Requires<[NoSLSBLRMitigation]>;
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
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} // isBranch, isTerminator, isBarrier, isIndirectBranch
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@ -1,149 +0,0 @@
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; RUN: llc -o - %s | FileCheck --check-prefix=SELDAG --check-prefix=CHECK %s
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; RUN: llc -global-isel -o - %s | FileCheck --check-prefix=GISEL --check-prefix=CHECK %s
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; TODO: support marker generation with GlobalISel
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-iphoneos"
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declare i8* @foo0(i32)
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declare i8* @foo1()
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declare void @llvm.objc.release(i8*)
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declare void @objc_object(i8*)
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declare void @foo2(i8*)
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
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declare %struct.S* @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(1))
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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%struct.S = type { i8 }
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@g = global i8* null, align 8
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@fptr = global i8* ()* null, align 8
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define i8* @rv_marker_1() {
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; CHECK-LABEL: rv_marker_1:
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; CHECK: .cfi_offset w30, -16
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; CHECK-NEXT: bl foo1
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; SELDAG-NEXT: mov x29, x29
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; GISEL-NOT: mov x29, x29
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;
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entry:
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%call = call "rv_marker" i8* @foo1()
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ret i8* %call
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}
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define void @rv_marker_2_select(i32 %c) {
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; CHECK-LABEL: rv_marker_2_select:
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; SELDAG: cinc w0, w8, eq
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; GISEL: csinc w0, w8, wzr, eq
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; CHECK-NEXT: bl foo0
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; SELDAG-NEXT: mov x29, x29
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; CHECK-NEXT: ldr x30, [sp], #16
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; CHECK-NEXT: b foo2
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;
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entry:
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%tobool.not = icmp eq i32 %c, 0
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%.sink = select i1 %tobool.not, i32 2, i32 1
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%call1 = call "rv_marker" i8* @foo0(i32 %.sink)
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tail call void @foo2(i8* %call1)
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ret void
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}
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define void @rv_marker_3() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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; CHECK-LABEL: rv_marker_3
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; CHECK: .cfi_offset w30, -32
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; CHECK-NEXT: bl foo1
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; SELDAG-NEXT: mov x29, x29
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;
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entry:
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%call = call "rv_marker" i8* @foo1()
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invoke void @objc_object(i8* %call) #5
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to label %invoke.cont unwind label %lpad
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invoke.cont: ; preds = %entry
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tail call void @llvm.objc.release(i8* %call)
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ret void
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lpad: ; preds = %entry
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%0 = landingpad { i8*, i32 }
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cleanup
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tail call void @llvm.objc.release(i8* %call)
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resume { i8*, i32 } %0
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}
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define void @rv_marker_4() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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; CHECK-LABEL: rv_marker_4
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; CHECK: .Ltmp3:
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; CHECK-NEXT: bl foo1
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; SELDAG-NEXT: mov x29, x29
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; CHECK-NEXT: .Ltmp4:
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;
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entry:
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%s = alloca %struct.S, align 1
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%0 = getelementptr inbounds %struct.S, %struct.S* %s, i64 0, i32 0
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call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %0) #2
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%call = invoke "rv_marker" i8* @foo1()
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to label %invoke.cont unwind label %lpad
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invoke.cont: ; preds = %entry
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invoke void @objc_object(i8* %call) #5
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to label %invoke.cont2 unwind label %lpad1
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invoke.cont2: ; preds = %invoke.cont
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tail call void @llvm.objc.release(i8* %call)
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%call3 = call %struct.S* @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(1) %s)
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call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %0)
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ret void
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lpad: ; preds = %entry
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%1 = landingpad { i8*, i32 }
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cleanup
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br label %ehcleanup
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lpad1: ; preds = %invoke.cont
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%2 = landingpad { i8*, i32 }
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cleanup
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tail call void @llvm.objc.release(i8* %call)
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br label %ehcleanup
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ehcleanup: ; preds = %lpad1, %lpad
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%.pn = phi { i8*, i32 } [ %2, %lpad1 ], [ %1, %lpad ]
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%call4 = call %struct.S* @_ZN1SD1Ev(%struct.S* nonnull dereferenceable(1) %s)
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call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %0)
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resume { i8*, i32 } %.pn
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}
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define i8* @rv_marker_5_indirect_call() {
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; CHECK-LABEL: rv_marker_5_indirect_call
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; CHECK: ldr [[ADDR:x[0-9]+]], [
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; CHECK-NEXT: blr [[ADDR]]
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; SLEDAG-NEXT: mov x29, x29
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; GISEL-NOT: mov x29, x29
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;
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entry:
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%0 = load i8* ()*, i8* ()** @fptr, align 8
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%call = call "rv_marker" i8* %0()
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tail call void @foo2(i8* %call)
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ret i8* %call
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}
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declare void @foo(i64, i64, i64)
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define void @rv_marker_multiarg(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: rv_marker_multiarg
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; CHECK: mov [[TMP:x[0-9]+]], x0
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; CHECK-NEXT: mov x0, x2
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; CHECK-NEXT: mov x2, [[TMP]]
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; CHECK-NEXT: bl foo
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; SELDAG-NEXT: mov x29, x29
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; GISEL-NOT: mov x29, x29
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call "rv_marker" void @foo(i64 %c, i64 %b, i64 %a)
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ret void
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}
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declare i32 @__gxx_personality_v0(...)
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@ -1,21 +0,0 @@
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# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=arm64-apple-ios -o - -emit-call-site-info %s | FileCheck %s
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# CHECK-LABEL: test_1_callsite_info
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# CHECK: bb.0.entry:
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# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit $x0, implicit $sp, implicit $fp, implicit $xzr {
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# CHECK-NEXT: BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
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# CHECK-NEXT: ORRXrs $fp, $xzr, $fp, 0
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# CHECK-NEXT: }
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# CHECK-NEXT: RET undef $lr, implicit killed $w0
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---
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name: test_1_callsite_info
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callSites:
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- {bb: 0, offset: 0, fwdArgRegs:
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- { arg: 0, reg: '$x0' } }
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body: |
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bb.0.entry:
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liveins: $lr, $x0
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BLR_RVMARKER $x0, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
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RET_ReallyLR implicit killed $w0
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...
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