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[Hexagon] Add a "generic" cpu

Add the generic processor for Hexagon so that it can be used
with 3rd party programs that create a back-end with the
"generic" CPU. This patch also enables the JIT for Hexagon.

Differential Revision: https://reviews.llvm.org/D48571

llvm-svn: 335641
This commit is contained in:
Brendon Cahoon 2018-06-26 18:44:05 +00:00
parent 5b2225c1d5
commit a4831b8a52
5 changed files with 14 additions and 1 deletions

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@ -322,6 +322,10 @@ class Proc<string Name, SchedMachineModel Model,
list<SubtargetFeature> Features>
: ProcessorModel<Name, Model, Features>;
def : Proc<"generic", HexagonModelV60,
[ArchV4, ArchV5, ArchV55, ArchV60,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv4", HexagonModelV4,
[ArchV4,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,

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@ -92,6 +92,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
{"generic", Hexagon::ArchEnum::V60},
{"hexagonv4", Hexagon::ArchEnum::V4},
{"hexagonv5", Hexagon::ArchEnum::V5},
{"hexagonv55", Hexagon::ArchEnum::V55},

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@ -309,6 +309,7 @@ static bool isCPUValid(std::string CPU)
{
std::vector<std::string> table
{
"generic",
"hexagonv4",
"hexagonv5",
"hexagonv55",

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@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
}
extern "C" void LLVMInitializeHexagonTargetInfo() {
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(
getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
}

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@ -0,0 +1,7 @@
; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s
; CHECK-NOT: invalid CPU
define i32 @test(i32 %a) {
ret i32 0
}