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[Hexagon] Add a "generic" cpu
Add the generic processor for Hexagon so that it can be used with 3rd party programs that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon. Differential Revision: https://reviews.llvm.org/D48571 llvm-svn: 335641
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@ -322,6 +322,10 @@ class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
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def : Proc<"generic", HexagonModelV60,
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[ArchV4, ArchV5, ArchV55, ArchV60,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv4", HexagonModelV4,
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[ArchV4,
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FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
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@ -92,6 +92,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
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HexagonSubtarget &
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HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
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static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
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{"generic", Hexagon::ArchEnum::V60},
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{"hexagonv4", Hexagon::ArchEnum::V4},
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{"hexagonv5", Hexagon::ArchEnum::V5},
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{"hexagonv55", Hexagon::ArchEnum::V55},
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@ -309,6 +309,7 @@ static bool isCPUValid(std::string CPU)
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{
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std::vector<std::string> table
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{
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"generic",
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"hexagonv4",
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"hexagonv5",
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"hexagonv55",
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@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
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}
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extern "C" void LLVMInitializeHexagonTargetInfo() {
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RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
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RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(
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getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
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}
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7
test/CodeGen/Hexagon/generic-cpu.ll
Normal file
7
test/CodeGen/Hexagon/generic-cpu.ll
Normal file
@ -0,0 +1,7 @@
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; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s
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; CHECK-NOT: invalid CPU
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define i32 @test(i32 %a) {
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ret i32 0
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}
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