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[X86][AVX512] Tag binop/rounding/sae instructions scheduler classes
llvm-svn: 319424
This commit is contained in:
parent
4b5d214bc5
commit
a48d538e18
@ -4107,16 +4107,16 @@ multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2)),
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itins.rr, IsCommutable>,
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AVX512BIBase, EVEX_4V;
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itins.rr, IsCommutable>, AVX512BIBase, EVEX_4V,
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Sched<[itins.Sched]>;
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defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1,
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(bitconvert (_.LdFrag addr:$src2)))),
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itins.rm>,
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AVX512BIBase, EVEX_4V;
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itins.rm>, AVX512BIBase, EVEX_4V,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -4130,8 +4130,8 @@ multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(_.VT (OpNode _.RC:$src1,
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(X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))),
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itins.rm>,
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AVX512BIBase, EVEX_4V, EVEX_B;
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itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -4236,14 +4236,14 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
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(_Src.VT _Src.RC:$src1),
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(_Src.VT _Src.RC:$src2))),
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itins.rr, IsCommutable>,
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AVX512BIBase, EVEX_4V;
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AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>;
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defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
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(ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
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(bitconvert (_Src.LdFrag addr:$src2)))),
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itins.rm>,
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AVX512BIBase, EVEX_4V;
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itins.rm>, AVX512BIBase, EVEX_4V,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
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(ins _Src.RC:$src1, _Brdct.ScalarMemOp:$src2),
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@ -4253,8 +4253,8 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
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(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
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(_Brdct.VT (X86VBroadcast
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(_Brdct.ScalarLdFrag addr:$src2)))))),
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itins.rm>,
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AVX512BIBase, EVEX_4V, EVEX_B;
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itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
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@ -4670,14 +4670,15 @@ multiclass avx512_comutable_binop_s<bits<8> opc, string OpcodeStr,
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(ins _.FRC:$src1, _.FRC:$src2),
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OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
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itins.rr> {
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itins.rr>, Sched<[itins.Sched]> {
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let isCommutable = 1;
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}
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def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.ScalarMemOp:$src2),
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OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.FRC:$dst, (OpNode _.FRC:$src1,
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(_.ScalarLdFrag addr:$src2)))], itins.rm>;
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(_.ScalarLdFrag addr:$src2)))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc,
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@ -4704,43 +4705,43 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpN
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2)), itins.rr,
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IsCommutable>, EVEX_4V;
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IsCommutable>, EVEX_4V, Sched<[itins.Sched]>;
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let mayLoad = 1 in {
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2)), itins.rm>,
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EVEX_4V;
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EVEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))),
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itins.rm>, EVEX_4V, EVEX_B;
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itins.rm>, EVEX_4V, EVEX_B,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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}
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multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
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X86VectorVTInfo _> {
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OpndItins itins, X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in
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defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
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"$rc, $src2, $src1", "$src1, $src2, $rc",
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
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EVEX_4V, EVEX_B, EVEX_RC;
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc))), itins.rr>,
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EVEX_4V, EVEX_B, EVEX_RC, Sched<[itins.Sched]>;
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}
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multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNodeRnd,
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X86VectorVTInfo _> {
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OpndItins itins, X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in
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defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
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EVEX_4V, EVEX_B;
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC))), itins.rr>,
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EVEX_4V, EVEX_B, Sched<[itins.Sched]>;
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}
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multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
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@ -4772,36 +4773,38 @@ multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDPatternOperator Op
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}
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}
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multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
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defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
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multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
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SizeItins itins> {
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defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, itins.s, v16f32_info>,
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EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
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defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, itins.d, v8f64_info>,
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EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
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}
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multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
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defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
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multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
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SizeItins itins> {
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defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, itins.s, v16f32_info>,
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EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
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defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, itins.d, v8f64_info>,
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EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
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}
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defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512,
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SSE_ALU_ITINS_P, 1>,
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avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
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avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SSE_ALU_ITINS_P>;
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defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512,
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SSE_MUL_ITINS_P, 1>,
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avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
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avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SSE_MUL_ITINS_P>;
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defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, SSE_ALU_ITINS_P>,
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avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
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avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SSE_ALU_ITINS_P>;
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defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, SSE_DIV_ITINS_P>,
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avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
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avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SSE_DIV_ITINS_P>;
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defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512,
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SSE_ALU_ITINS_P, 0>,
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avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
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avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd, SSE_ALU_ITINS_P>;
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defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512,
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SSE_ALU_ITINS_P, 0>,
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avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
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avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd, SSE_ALU_ITINS_P>;
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let isCodeGenOnly = 1 in {
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defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512,
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SSE_ALU_ITINS_P, 1>;
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@ -4922,64 +4925,69 @@ let Predicates = [HasVLX,HasDQI] in {
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}
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multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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OpndItins itins, X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in {
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defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT))),
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itins.rr>, EVEX_4V, Sched<[itins.Sched]>;
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT)),
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itins.rm>, EVEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
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EVEX_4V, EVEX_B;
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(_.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT)), itins.rm>,
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EVEX_4V, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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OpndItins itins, X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain in {
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defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT))), itins.rr>,
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Sched<[itins.Sched]>;
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defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, _.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT))>;
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(i32 FROUND_CURRENT)), itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode, SDNode OpNodeScal> {
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defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
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defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F32P, v16f32_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, SSE_ALU_F32P, v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
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defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F64P, v8f64_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, SSE_ALU_F64P, v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f32x_info>,
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defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, SSE_ALU_F32S, f32x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, SSE_ALU_ITINS_S.s>,
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EVEX_4V,EVEX_CD8<32, CD8VT1>;
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defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f64x_info>,
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defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, SSE_ALU_F64S, f64x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, SSE_ALU_ITINS_S.d>,
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EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
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// Define only if AVX512VL feature is present.
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let Predicates = [HasVLX] in {
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defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
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defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F32P, v4f32x_info>,
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EVEX_V128, EVEX_CD8<32, CD8VF>;
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defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
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defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F32P, v8f32x_info>,
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EVEX_V256, EVEX_CD8<32, CD8VF>;
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defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
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defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F64P, v2f64x_info>,
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EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
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defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
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defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, SSE_ALU_F64P, v4f64x_info>,
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EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
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}
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}
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||||
@ -7688,40 +7696,42 @@ defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt">,
|
||||
|
||||
defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
|
||||
|
||||
multiclass
|
||||
avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
|
||||
|
||||
multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
|
||||
OpndItins itins, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in {
|
||||
defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
|
||||
"$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
|
||||
(i32 imm:$src3)))>;
|
||||
(i32 imm:$src3))), itins.rr>,
|
||||
Sched<[itins.Sched]>;
|
||||
|
||||
defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
|
||||
"$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
|
||||
(_.VT (X86RndScalesRnd (_.VT _.RC:$src1), (_.VT _.RC:$src2),
|
||||
(i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
|
||||
(i32 imm:$src3), (i32 FROUND_NO_EXC))), itins.rr>, EVEX_B,
|
||||
Sched<[itins.Sched]>;
|
||||
|
||||
defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr,
|
||||
"$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(_.VT (X86RndScales _.RC:$src1,
|
||||
_.ScalarIntMemCPat:$src2, (i32 imm:$src3)))>;
|
||||
_.ScalarIntMemCPat:$src2, (i32 imm:$src3))), itins.rm>,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
|
||||
let isCodeGenOnly = 1, hasSideEffects = 0 in {
|
||||
def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
|
||||
(ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
|
||||
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
||||
[]>;
|
||||
[], itins.rr>, Sched<[itins.Sched]>;
|
||||
|
||||
let mayLoad = 1 in
|
||||
def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
|
||||
(ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
||||
[]>;
|
||||
[], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -7762,11 +7772,12 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
|
||||
}
|
||||
}
|
||||
|
||||
defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
|
||||
AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", SSE_ALU_F32S,
|
||||
f32x_info>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
|
||||
AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
|
||||
defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", SSE_ALU_F64S,
|
||||
f64x_info>, VEX_W, AVX512AIi8Base, EVEX_4V,
|
||||
EVEX_CD8<64, CD8VT1>;
|
||||
|
||||
//-------------------------------------------------
|
||||
// Integer truncate and extend operations
|
||||
@ -8593,30 +8604,33 @@ defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
|
||||
// op(broadcast(eltVt),imm)
|
||||
//all instruction created with FROUND_CURRENT
|
||||
multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86VectorVTInfo _>{
|
||||
OpndItins itins, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in {
|
||||
defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(i32 imm:$src2))>;
|
||||
(i32 imm:$src2)), itins.rr>, Sched<[itins.Sched]>;
|
||||
defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.MemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
|
||||
(i32 imm:$src2))>;
|
||||
(i32 imm:$src2)), itins.rm>,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
|
||||
"${src1}"##_.BroadcastStr##", $src2",
|
||||
(OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
|
||||
(i32 imm:$src2))>, EVEX_B;
|
||||
(i32 imm:$src2)), itins.rm>, EVEX_B,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
}
|
||||
}
|
||||
|
||||
//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
|
||||
multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, X86VectorVTInfo _>{
|
||||
SDNode OpNode, OpndItins itins,
|
||||
X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
@ -8624,22 +8638,24 @@ multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
"$src1, {sae}, $src2",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(i32 imm:$src2),
|
||||
(i32 FROUND_NO_EXC))>, EVEX_B;
|
||||
(i32 FROUND_NO_EXC)), itins.rr>,
|
||||
EVEX_B, Sched<[itins.Sched]>;
|
||||
}
|
||||
|
||||
multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
|
||||
AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode,
|
||||
SDNode OpNodeRnd, Predicate prd>{
|
||||
SDNode OpNodeRnd, OpndItins itins, Predicate prd>{
|
||||
let Predicates = [prd] in {
|
||||
defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
|
||||
avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd, _.info512>,
|
||||
EVEX_V512;
|
||||
defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, itins,
|
||||
_.info512>,
|
||||
avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd,
|
||||
itins, _.info512>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [prd, HasVLX] in {
|
||||
defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
|
||||
EVEX_V128;
|
||||
defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
|
||||
EVEX_V256;
|
||||
defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, itins,
|
||||
_.info128>, EVEX_V128;
|
||||
defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, itins,
|
||||
_.info256>, EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
@ -8648,27 +8664,30 @@ multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
|
||||
// op(reg_vec2,broadcast(eltVt),imm)
|
||||
//all instruction created with FROUND_CURRENT
|
||||
multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86VectorVTInfo _>{
|
||||
OpndItins itins, X86VectorVTInfo _>{
|
||||
let ExeDomain = _.ExeDomain in {
|
||||
defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(i32 imm:$src3))>;
|
||||
(i32 imm:$src3)), itins.rr>,
|
||||
Sched<[itins.Sched]>;
|
||||
defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT (bitconvert (_.LdFrag addr:$src2))),
|
||||
(i32 imm:$src3))>;
|
||||
(i32 imm:$src3)), itins.rm>,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr##", $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
|
||||
(i32 imm:$src3))>, EVEX_B;
|
||||
(i32 imm:$src3)), itins.rm>, EVEX_B,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -8717,27 +8736,30 @@ multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
|
||||
// op(reg_vec2,mem_scalar,imm)
|
||||
multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86VectorVTInfo _> {
|
||||
OpndItins itins, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in {
|
||||
defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(i32 imm:$src3))>;
|
||||
(i32 imm:$src3)), itins.rr>,
|
||||
Sched<[itins.Sched]>;
|
||||
defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT (scalar_to_vector
|
||||
(_.ScalarLdFrag addr:$src2))),
|
||||
(i32 imm:$src3))>;
|
||||
(i32 imm:$src3)), itins.rm>,
|
||||
Sched<[itins.Sched.Folded, ReadAfterLd]>;
|
||||
}
|
||||
}
|
||||
|
||||
//handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
|
||||
multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, X86VectorVTInfo _>{
|
||||
SDNode OpNode, OpndItins itins,
|
||||
X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
|
||||
@ -8746,11 +8768,13 @@ multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(i32 imm:$src3),
|
||||
(i32 FROUND_NO_EXC))>, EVEX_B;
|
||||
(i32 FROUND_NO_EXC)), itins.rr>,
|
||||
EVEX_B, Sched<[itins.Sched]>;
|
||||
}
|
||||
|
||||
//handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
|
||||
multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, X86VectorVTInfo _> {
|
||||
multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
OpndItins itins, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
|
||||
@ -8759,22 +8783,23 @@ multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(i32 imm:$src3),
|
||||
(i32 FROUND_NO_EXC))>, EVEX_B;
|
||||
(i32 FROUND_NO_EXC)), itins.rr>,
|
||||
EVEX_B, Sched<[itins.Sched]>;
|
||||
}
|
||||
|
||||
multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
|
||||
AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode,
|
||||
SDNode OpNodeRnd, Predicate prd>{
|
||||
SDNode OpNodeRnd, OpndItins itins, Predicate prd>{
|
||||
let Predicates = [prd] in {
|
||||
defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
|
||||
avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd, _.info512>,
|
||||
defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, itins, _.info512>,
|
||||
avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNodeRnd, itins, _.info512>,
|
||||
EVEX_V512;
|
||||
|
||||
}
|
||||
let Predicates = [prd, HasVLX] in {
|
||||
defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
|
||||
defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, itins, _.info128>,
|
||||
EVEX_V128;
|
||||
defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
|
||||
defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, itins, _.info256>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
@ -8808,68 +8833,62 @@ multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
|
||||
|
||||
multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
|
||||
X86VectorVTInfo _, bits<8> opc, SDNode OpNode,
|
||||
SDNode OpNodeRnd, Predicate prd>{
|
||||
SDNode OpNodeRnd, OpndItins itins, Predicate prd>{
|
||||
let Predicates = [prd] in {
|
||||
defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
|
||||
avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNodeRnd, _>;
|
||||
defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, itins, _>,
|
||||
avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNodeRnd, itins, _>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
|
||||
bits<8> opcPs, bits<8> opcPd, SDNode OpNode,
|
||||
SDNode OpNodeRnd, Predicate prd>{
|
||||
SDNode OpNodeRnd, SizeItins itins, Predicate prd>{
|
||||
defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
|
||||
opcPs, OpNode, OpNodeRnd, prd>, EVEX_CD8<32, CD8VF>;
|
||||
opcPs, OpNode, OpNodeRnd, itins.s, prd>,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
|
||||
opcPd, OpNode, OpNodeRnd, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
opcPd, OpNode, OpNodeRnd, itins.d, prd>,
|
||||
EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
}
|
||||
|
||||
|
||||
defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
|
||||
X86VReduce, X86VReduceRnd, HasDQI>,
|
||||
X86VReduce, X86VReduceRnd, SSE_ALU_ITINS_P, HasDQI>,
|
||||
AVX512AIi8Base, EVEX;
|
||||
defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
|
||||
X86VRndScale, X86VRndScaleRnd, HasAVX512>,
|
||||
X86VRndScale, X86VRndScaleRnd, SSE_ALU_ITINS_P, HasAVX512>,
|
||||
AVX512AIi8Base, EVEX;
|
||||
defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
|
||||
X86VGetMant, X86VGetMantRnd, HasAVX512>,
|
||||
X86VGetMant, X86VGetMantRnd, SSE_ALU_ITINS_P, HasAVX512>,
|
||||
AVX512AIi8Base, EVEX;
|
||||
|
||||
|
||||
defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
|
||||
0x50, X86VRange,
|
||||
X86VRangeRnd, HasDQI>,
|
||||
0x50, X86VRange, X86VRangeRnd,
|
||||
SSE_ALU_F64P, HasDQI>,
|
||||
AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
|
||||
0x50, X86VRange,
|
||||
X86VRangeRnd, HasDQI>,
|
||||
0x50, X86VRange, X86VRangeRnd,
|
||||
SSE_ALU_F32P, HasDQI>,
|
||||
AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
|
||||
0x51, X86Ranges, X86RangesRnd,
|
||||
HasDQI>,
|
||||
defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd",
|
||||
f64x_info, 0x51, X86Ranges, X86RangesRnd, SSE_ALU_F64S, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
|
||||
0x51, X86Ranges, X86RangesRnd,
|
||||
HasDQI>,
|
||||
0x51, X86Ranges, X86RangesRnd, SSE_ALU_F32S, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
|
||||
0x57, X86Reduces,
|
||||
X86ReducesRnd, HasDQI>,
|
||||
0x57, X86Reduces, X86ReducesRnd, SSE_ALU_F64S, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
|
||||
0x57, X86Reduces,
|
||||
X86ReducesRnd, HasDQI>,
|
||||
0x57, X86Reduces, X86ReducesRnd, SSE_ALU_F32S, HasDQI>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
|
||||
0x27, X86GetMants,
|
||||
X86GetMantsRnd, HasAVX512>,
|
||||
0x27, X86GetMants, X86GetMantsRnd, SSE_ALU_F64S, HasAVX512>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
|
||||
0x27, X86GetMants,
|
||||
X86GetMantsRnd, HasAVX512>,
|
||||
0x27, X86GetMants, X86GetMantsRnd, SSE_ALU_F32S, HasAVX512>,
|
||||
AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
|
||||
|
||||
let Predicates = [HasAVX512] in {
|
||||
|
Loading…
Reference in New Issue
Block a user