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https://github.com/RPCS3/llvm-mirror.git
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[GlobalISel][AArch64] Add generic legalization rule for extends
This adds a legalization rule for G_ZEXT, G_ANYEXT, and G_SEXT which allows extends whenever the types will fit in registers (or the source is an s1). Update tests. Add GISel checks throughout all of arm64-vabs.ll, where we now select a good portion of the code. Add GISel checks to arm64-subvector-extend.ll, which has a good number of vector extends in it. Differential Revision: https://reviews.llvm.org/D60889 llvm-svn: 359222
This commit is contained in:
Jessica Paquette
parent
cc04ae157c
commit
a49fa69bbb
@ -321,8 +321,29 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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// Extensions
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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.legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32})
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.legalFor({v8s16, v8s8});
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.legalIf([=](const LegalityQuery &Query) {
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unsigned DstSize = Query.Types[0].getSizeInBits();
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// Make sure that we have something that will fit in a register, and
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// make sure it's a power of 2.
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if (DstSize < 8 || DstSize > 128 || !isPowerOf2_32(DstSize))
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return false;
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const LLT &SrcTy = Query.Types[1];
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// Special case for s1.
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if (SrcTy == s1)
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return true;
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// Make sure we fit in a register otherwise. Don't bother checking that
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// the source type is below 128 bits. We shouldn't be allowing anything
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// through which is wider than the destination in the first place.
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unsigned SrcSize = SrcTy.getSizeInBits();
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if (SrcSize < 8 || !isPowerOf2_32(SrcSize))
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return false;
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return true;
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});
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getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
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@ -227,3 +227,140 @@ body: |
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%2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_zext_v4s32_from_v4s16
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_zext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
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; CHECK: $q0 = COPY [[ZEXT]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_sext_v4s32_from_v4s16
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_sext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
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; CHECK: $q0 = COPY [[SEXT]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s32>) = G_SEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_anyext_v4s32_from_v4s16
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_anyext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
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; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_zext_v2s64_from_v2s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_zext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
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; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_sext_v2s64_from_v2s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_sext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
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; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s64>) = G_SEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_anyext_v2s64_from_v2s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_anyext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
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; CHECK: $q0 = COPY [[ANYEXT]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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@ -157,7 +157,7 @@
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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#
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# DEBUG-NEXT: G_ANYEXT (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. the first uncovered type index: 2, OK
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_TRUNC (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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@ -175,10 +175,10 @@
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# DEBUG: .. the first uncovered type index: 2, OK
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#
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# DEBUG-NEXT: G_SEXT (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. the first uncovered type index: 2, OK
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_ZEXT (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. the first uncovered type index: 2, OK
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_SHL (opcode {{[0-9]+}}): 2 type indices
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# DEBUG:.. type index coverage check SKIPPED: user-defined predicate detected
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@ -7,18 +7,24 @@
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define void @anyext_s64_from_s32() { ret void }
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define void @anyext_s32_from_s8() { ret void }
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define void @anyext_v8s16_from_v8s8() { ret void }
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define void @anyext_v4s32_from_v4s16() { ret void }
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define void @anyext_v2s64_from_v2s32() { ret void }
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define void @zext_s64_from_s32() { ret void }
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define void @zext_s32_from_s16() { ret void }
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define void @zext_s32_from_s8() { ret void }
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define void @zext_s16_from_s8() { ret void }
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define void @zext_v8s16_from_v8s8() { ret void }
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define void @zext_v4s32_from_v4s16() { ret void }
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define void @zext_v2s64_from_v2s32() { ret void }
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define void @sext_s64_from_s32() { ret void }
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define void @sext_s32_from_s16() { ret void }
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define void @sext_s32_from_s8() { ret void }
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define void @sext_s16_from_s8() { ret void }
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define void @sext_v8s16_from_v8s8() { ret void }
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define void @sext_v4s32_from_v4s16() { ret void }
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define void @sext_v2s64_from_v2s32() { ret void }
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...
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---
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@ -90,6 +96,60 @@ body: |
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%1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: anyext_v4s32_from_v4s16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: anyext_v2s64_from_v2s32
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alignment: 2
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tracksRegLiveness: true
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: anyext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: zext_s64_from_s32
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@ -212,6 +272,58 @@ body: |
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...
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---
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name: zext_v4s32_from_v4s16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: zext_v2s64_from_v2s32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: zext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[USHLLv2i32_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_s64_from_s32
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legalized: true
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@ -332,3 +444,54 @@ body: |
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_v4s32_from_v4s16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: sext_v4s32_from_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[SSHLLv4i16_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: sext_v2s64_from_v2s32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: sext_v2s64_from_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
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; CHECK: $q0 = COPY [[SSHLLv2i32_shift]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
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; Test efficient codegen of vector extends up from legal type to 128 bit
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; and 256 bit vector types.
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@ -6,6 +7,8 @@
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;-----
|
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; Vectors of i16.
|
||||
;-----
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}}(in function: func1)
|
||||
define <8 x i16> @func1(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func1:
|
||||
; CHECK-NEXT: ushll.8h v0, v0, #0
|
||||
@ -14,6 +17,7 @@ define <8 x i16> @func1(<8 x i8> %v0) nounwind {
|
||||
ret <8 x i16> %r
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}}(in function: func2)
|
||||
define <8 x i16> @func2(<8 x i8> %v0) nounwind {
|
||||
; CHECK-LABEL: func2:
|
||||
; CHECK-NEXT: sshll.8h v0, v0, #0
|
||||
@ -44,6 +48,7 @@ define <16 x i16> @func4(<16 x i8> %v0) nounwind {
|
||||
; Vectors of i32.
|
||||
;-----
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}}(in function: afunc1)
|
||||
define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc1:
|
||||
; CHECK-NEXT: ushll.4s v0, v0, #0
|
||||
@ -52,6 +57,7 @@ define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}}(in function: afunc2)
|
||||
define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
|
||||
; CHECK-LABEL: afunc2:
|
||||
; CHECK-NEXT: sshll.4s v0, v0, #0
|
||||
|
||||
@ -1,13 +1,11 @@
|
||||
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
|
||||
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL,FALLBACK
|
||||
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=FALLBACK,CHECK
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}}(<8 x s16>) = G_ZEXT %4:_(<8 x s8>)
|
||||
; FALLBACK-NOT: remark:{{.*}} G_ZEXT
|
||||
; FALLBACK-NOT: remark:{{.*}} sabdl8h
|
||||
define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK-LABEL: sabdl8h:
|
||||
;CHECK: sabdl.8h
|
||||
;GISEL-LABEL: sabdl8h:
|
||||
;GISEL: sabdl.8h
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
||||
@ -15,6 +13,7 @@ define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} sabdl4s
|
||||
define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK-LABEL: sabdl4s:
|
||||
;CHECK: sabdl.4s
|
||||
@ -25,6 +24,7 @@ define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} sabdl2d
|
||||
define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK-LABEL: sabdl2d:
|
||||
;CHECK: sabdl.2d
|
||||
@ -71,6 +71,7 @@ define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
||||
ret <2 x i64> %tmp4
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabdl8h)
|
||||
define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK-LABEL: uabdl8h:
|
||||
;CHECK: uabdl.8h
|
||||
@ -81,6 +82,7 @@ define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
ret <8 x i16> %tmp4
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabdl4s)
|
||||
define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
;CHECK-LABEL: uabdl4s:
|
||||
;CHECK: uabdl.4s
|
||||
@ -91,6 +93,7 @@ define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabdl2d)
|
||||
define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
;CHECK-LABEL: uabdl2d:
|
||||
;CHECK: uabdl.2d
|
||||
@ -560,6 +563,7 @@ declare <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32>) nounwind readnone
|
||||
declare <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64>) nounwind readnone
|
||||
declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} sabal8h
|
||||
define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
|
||||
;CHECK-LABEL: sabal8h:
|
||||
;CHECK: sabal.8h
|
||||
@ -572,6 +576,7 @@ define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} sabal4s
|
||||
define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
|
||||
;CHECK-LABEL: sabal4s:
|
||||
;CHECK: sabal.4s
|
||||
@ -584,6 +589,7 @@ define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} sabal2d
|
||||
define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
|
||||
;CHECK-LABEL: sabal2d:
|
||||
;CHECK: sabal.2d
|
||||
@ -639,6 +645,7 @@ define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwin
|
||||
ret <2 x i64> %tmp5
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabal8h
|
||||
define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
|
||||
;CHECK-LABEL: uabal8h:
|
||||
;CHECK: uabal.8h
|
||||
@ -651,6 +658,7 @@ define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
|
||||
ret <8 x i16> %tmp5
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabal8s
|
||||
define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
|
||||
;CHECK-LABEL: uabal4s:
|
||||
;CHECK: uabal.4s
|
||||
@ -663,6 +671,7 @@ define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind
|
||||
ret <4 x i32> %tmp5
|
||||
}
|
||||
|
||||
; FALLBACK-NOT: remark:{{.*}} uabal2d
|
||||
define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
|
||||
;CHECK-LABEL: uabal2d:
|
||||
;CHECK: uabal.2d
|
||||
|
||||
Loading…
Reference in New Issue
Block a user