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Fix address mode 3 immediate offset mode encoding.

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llvm-svn: 59109
This commit is contained in:
Evan Cheng 2008-11-12 07:34:37 +00:00
parent 7fef8cfe75
commit a4dc0e304e
2 changed files with 7 additions and 5 deletions
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10
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -736,11 +736,11 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
// Set bit[3:0] to the corresponding Rm register
Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
// if this instr is in scaled register offset/index instruction, set
// If this instr is in scaled register offset/index instruction, set
// shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
Binary |= getShiftOp(AM2Opc) << 5; // shift
Binary |= ShImm << 7; // shift_immed
Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
Binary |= ShImm << ARMII::ShiftShift; // shift_immed
}
emitWordLE(Binary);
@ -792,8 +792,8 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
Binary |= 1 << ARMII::AM3_I_BitShift;
if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
// Set operands
Binary |= (ImmOffs >> 4) << 8; // immedH
Binary |= (ImmOffs & ~0xF); // immedL
Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
Binary |= (ImmOffs & 0xF); // immedL
}
emitWordLE(Binary);

2
lib/Target/ARM/ARMInstrInfo.h
View File

@ -116,8 +116,10 @@ namespace ARMII {
// Field shifts - such shifts are used to set field while generating
// machine instructions.
M_BitShift = 5,
ShiftImmShift = 5,
ShiftShift = 7,
N_BitShift = 7,
ImmHiShift = 8,
SoRotImmShift = 8,
RegRsShift = 8,
ExtRotImmShift = 10,