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[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in X86TargetParser.def.

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These represent the same thing but 64BIT only showed up from
getHostCPUFeatures providing a list of featuers to clang. While
EM64T showed up from getting the features for a named CPU.

EM64T didn't have a string specifically so it would not be passed
up to clang when getting features for a named CPU. While 64bit
needed a name since that's how it is index.

Merge them by filtering 64bit out before sending features to clang
for named CPUs.
This commit is contained in:
Craig Topper 2020-07-07 17:55:07 -07:00
parent 581ce5f5c9
commit a5195d9d77
4 changed files with 30 additions and 28 deletions
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4
include/llvm/Support/X86TargetParser.def
View File

@ -184,10 +184,6 @@ X86_FEATURE (CLWB, "clwb")
X86_FEATURE (CLZERO, "clzero")
X86_FEATURE (CMPXCHG16B, "cx16")
X86_FEATURE (CMPXCHG8B, "cx8")
// FIXME: Merge with 64BIT? Currently separate to be used to tell if CPU is
// valid for 64-bit mode, but has empty string so it doesn't get added to
// target attributes in IR.
X86_FEATURE (EM64T, "")
X86_FEATURE (ENQCMD, "enqcmd")
X86_FEATURE (F16C, "f16c")
X86_FEATURE (FSGSBASE, "fsgsbase")

5
lib/Analysis/InstructionSimplify.cpp
View File

@ -4117,11 +4117,6 @@ static Value *SimplifySelectInst(Value *Cond, Value *TrueVal, Value *FalseVal,
if (TrueVal == FalseVal)
return TrueVal;
if (isa<UndefValue>(TrueVal)) // select ?, undef, X -> X
return FalseVal;
if (isa<UndefValue>(FalseVal)) // select ?, X, undef -> X
return TrueVal;
// Deal with partial undef vector constants: select ?, VecC, VecC' --> VecC''
Constant *TrueC, *FalseC;
if (TrueVal->getType()->isVectorTy() && match(TrueVal, m_Constant(TrueC)) &&

6
lib/Support/Host.cpp
View File

@ -868,7 +868,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
}
break;
}
if (testFeature(X86::FEATURE_EM64T)) {
if (testFeature(X86::FEATURE_64BIT)) {
*Type = X86::INTEL_CORE2; // "core2"
*Subtype = X86::INTEL_CORE2_65;
break;
@ -894,7 +894,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
}
break;
case 15: {
if (testFeature(X86::FEATURE_EM64T)) {
if (testFeature(X86::FEATURE_64BIT)) {
*Type = X86::INTEL_NOCONA;
break;
}
@ -1140,7 +1140,7 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
setFeature(X86::FEATURE_FMA4);
if (HasExtLeaf1 && ((EDX >> 29) & 1))
setFeature(X86::FEATURE_EM64T);
setFeature(X86::FEATURE_64BIT);
}
StringRef sys::getHostCPUName() {

43
lib/Support/X86TargetParser.cpp
View File

@ -48,6 +48,14 @@ public:
return (Bits[I / 32] & Mask) != 0;
}
constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
uint32_t NewBits = Bits[I] & RHS.Bits[I];
Bits[I] = NewBits;
}
return *this;
}
constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
uint32_t NewBits = Bits[I] | RHS.Bits[I];
@ -57,16 +65,14 @@ public:
}
constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
FeatureBitset Result;
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
Result.Bits[I] = Bits[I] & RHS.Bits[I];
FeatureBitset Result = *this;
Result &= RHS;
return Result;
}
constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
FeatureBitset Result;
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
Result.Bits[I] = Bits[I] | RHS.Bits[I];
FeatureBitset Result = *this;
Result |= RHS;
return Result;
}
@ -111,10 +117,10 @@ static constexpr FeatureBitset FeaturesPentium4 =
static constexpr FeatureBitset FeaturesPrescott =
FeaturesPentium4 | FeatureSSE3;
static constexpr FeatureBitset FeaturesNocona =
FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B;
FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
// Basic 64-bit capable CPU.
static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T;
static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
// Intel Core CPUs
static constexpr FeatureBitset FeaturesCore2 =
@ -201,7 +207,7 @@ static constexpr FeatureBitset FeaturesAthlon =
static constexpr FeatureBitset FeaturesAthlonXP =
FeaturesAthlon | FeatureFXSR | FeatureSSE;
static constexpr FeatureBitset FeaturesK8 =
FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T;
FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
static constexpr FeatureBitset FeaturesAMDFAM10 =
FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
@ -209,7 +215,7 @@ static constexpr FeatureBitset FeaturesAMDFAM10 =
// Bobcat architecture processors.
static constexpr FeatureBitset FeaturesBTVER1 =
FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T |
FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
FeatureSAHF;
@ -220,7 +226,7 @@ static constexpr FeatureBitset FeaturesBTVER2 =
// AMD Bulldozer architecture processors.
static constexpr FeatureBitset FeaturesBDVER1 =
FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | FeatureLWP |
FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
@ -236,7 +242,7 @@ static constexpr FeatureBitset FeaturesBDVER4 =
static constexpr FeatureBitset FeaturesZNVER1 =
FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C |
FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
@ -363,7 +369,7 @@ static constexpr ProcInfo Processors[] = {
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
for (const auto &P : Processors)
if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit))
if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
return P.Kind;
return CK_None;
@ -372,7 +378,7 @@ X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
bool Only64Bit) {
for (const auto &P : Processors)
if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit))
if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
Values.emplace_back(P.Name);
}
@ -401,7 +407,6 @@ static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
static constexpr FeatureBitset ImpliedFeaturesEM64T = {};
static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
@ -528,8 +533,14 @@ void llvm::X86::getFeaturesForCPU(StringRef CPU,
[&](const ProcInfo &P) { return P.Name == CPU; });
assert(I != std::end(Processors) && "Processor not found!");
FeatureBitset Bits = I->Features;
// Remove the 64-bit feature which we only use to validate if a CPU can
// be used with 64-bit mode.
Bits &= ~Feature64BIT;
// Add the string version of all set bits.
getFeatureBitsAsStrings(I->Features, EnabledFeatures);
getFeatureBitsAsStrings(Bits, EnabledFeatures);
}
// For each feature that is (transitively) implied by this feature, set it.