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https://github.com/RPCS3/llvm-mirror.git
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R600: Use LDS and vectors for private memory
llvm-svn: 211110
This commit is contained in:
Tom Stellard
parent
4bdc400436
commit
a529beed9c
@ -17,6 +17,7 @@
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namespace llvm {
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class AMDGPUInstrPrinter;
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class AMDGPUSubtarget;
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class AMDGPUTargetMachine;
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class FunctionPass;
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class MCAsmInfo;
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@ -47,6 +48,7 @@ void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST);
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
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@ -86,28 +86,40 @@ def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
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def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
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def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
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class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
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"localmemorysize"#Value,
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"LocalMemorySize",
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!cast<string>(Value),
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"The size of local memory in bytes">;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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Value#" GPU generation", Implies>;
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def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
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def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
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def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
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def FeatureR600 : SubtargetFeatureGeneration<"R600",
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[FeatureR600ALUInst, FeatureFetchLimit8]>;
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[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
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def FeatureR700 : SubtargetFeatureGeneration<"R700",
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[FeatureFetchLimit16]>;
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[FeatureFetchLimit16, FeatureLocalMemorySize0]>;
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def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
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[FeatureFetchLimit16]>;
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[FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
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def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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[FeatureFetchLimit16, FeatureWavefrontSize64]>;
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[FeatureFetchLimit16, FeatureWavefrontSize64,
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FeatureLocalMemorySize32768]
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>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[Feature64BitPtr, FeatureFP64]>;
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768]>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64]>;
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[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536]>;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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@ -258,6 +258,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
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}
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case ISD::SCALAR_TO_VECTOR:
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case AMDGPUISD::BUILD_VERTICAL_VECTOR:
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case ISD::BUILD_VECTOR: {
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unsigned RegClassID;
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const AMDGPURegisterInfo *TRI =
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@ -308,7 +309,12 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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// can't be bundled by our scheduler.
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switch(NumVectorElts) {
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case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
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case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
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case 4:
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if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
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RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
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else
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RegClassID = AMDGPU::R600_Reg128RegClassID;
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break;
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default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
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}
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}
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@ -1911,6 +1911,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(CVT_F32_UBYTE1)
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NODE_NAME_CASE(CVT_F32_UBYTE2)
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NODE_NAME_CASE(CVT_F32_UBYTE3)
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NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
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NODE_NAME_CASE(STORE_MSKOR)
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NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
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}
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@ -203,6 +203,15 @@ enum {
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CVT_F32_UBYTE1,
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CVT_F32_UBYTE2,
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CVT_F32_UBYTE3,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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/// |X |Y|Z|W|
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/// T0|v.x| | | |
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/// T1|v.y| | | |
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/// T2|v.z| | | |
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/// T3|v.w| | | |
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BUILD_VERTICAL_VECTOR,
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FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
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STORE_MSKOR,
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LOAD_CONSTANT,
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365
lib/Target/R600/AMDGPUPromoteAlloca.cpp
Normal file
365
lib/Target/R600/AMDGPUPromoteAlloca.cpp
Normal file
@ -0,0 +1,365 @@
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//===-- AMDGPUPromoteAlloca.cpp - Promote Allocas -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates allocas by either converting them into vectors or
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// by migrating them to local address space.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "amdgpu-promote-alloca"
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using namespace llvm;
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namespace {
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class AMDGPUPromoteAlloca : public FunctionPass,
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public InstVisitor<AMDGPUPromoteAlloca> {
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static char ID;
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Module *Mod;
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const AMDGPUSubtarget &ST;
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int LocalMemAvailable;
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public:
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AMDGPUPromoteAlloca(const AMDGPUSubtarget &st) : FunctionPass(ID), ST(st),
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LocalMemAvailable(0) { }
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virtual bool doInitialization(Module &M);
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virtual bool runOnFunction(Function &F);
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virtual const char *getPassName() const {
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return "AMDGPU Promote Alloca";
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}
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void visitAlloca(AllocaInst &I);
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};
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} // End anonymous namespace
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char AMDGPUPromoteAlloca::ID = 0;
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bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
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Mod = &M;
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return false;
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}
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bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
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const FunctionType *FTy = F.getFunctionType();
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LocalMemAvailable = ST.getLocalMemorySize();
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// If the function has any arguments in the local address space, then it's
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// possible these arguments require the entire local memory space, so
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// we cannot use local memory in the pass.
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for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) {
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const Type *ParamTy = FTy->getParamType(i);
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if (ParamTy->isPointerTy() &&
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ParamTy->getPointerAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
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LocalMemAvailable = 0;
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DEBUG(dbgs() << "Function has local memory argument. Promoting to "
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"local memory disabled.\n");
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break;
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}
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}
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if (LocalMemAvailable > 0) {
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// Check how much local memory is being used by global objects
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for (Module::global_iterator I = Mod->global_begin(),
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E = Mod->global_end(); I != E; ++I) {
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GlobalVariable *GV = I;
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PointerType *GVTy = GV->getType();
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if (GVTy->getAddressSpace() != AMDGPUAS::LOCAL_ADDRESS)
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continue;
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for (Value::use_iterator U = GV->use_begin(),
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UE = GV->use_end(); U != UE; ++U) {
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Instruction *Use = dyn_cast<Instruction>(*U);
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if (!Use)
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continue;
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if (Use->getParent()->getParent() == &F)
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LocalMemAvailable -=
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Mod->getDataLayout()->getTypeAllocSize(GVTy->getElementType());
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}
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}
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}
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LocalMemAvailable = std::max(0, LocalMemAvailable);
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DEBUG(dbgs() << LocalMemAvailable << "bytes free in local memory.\n");
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visit(F);
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return false;
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}
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static VectorType *arrayTypeToVecType(const Type *ArrayTy) {
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return VectorType::get(ArrayTy->getArrayElementType(),
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ArrayTy->getArrayNumElements());
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}
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static Value* calculateVectorIndex(Value *Ptr,
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std::map<GetElementPtrInst*, Value*> GEPIdx) {
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if (isa<AllocaInst>(Ptr))
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return Constant::getNullValue(Type::getInt32Ty(Ptr->getContext()));
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GetElementPtrInst *GEP = cast<GetElementPtrInst>(Ptr);
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return GEPIdx[GEP];
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}
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static Value* GEPToVectorIndex(GetElementPtrInst *GEP) {
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// FIXME we only support simple cases
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if (GEP->getNumOperands() != 3)
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return NULL;
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ConstantInt *I0 = dyn_cast<ConstantInt>(GEP->getOperand(1));
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if (!I0 || !I0->isZero())
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return NULL;
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return GEP->getOperand(2);
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}
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static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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Type *AllocaTy = Alloca->getAllocatedType();
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DEBUG(dbgs() << "Alloca Candidate for vectorization \n");
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// FIXME: There is no reason why we can't support larger arrays, we
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// are just being conservative for now.
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if (!AllocaTy->isArrayTy() ||
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AllocaTy->getArrayElementType()->isVectorTy() ||
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AllocaTy->getArrayNumElements() > 4) {
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DEBUG(dbgs() << " Cannot convert type to vector");
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return false;
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}
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std::map<GetElementPtrInst*, Value*> GEPVectorIdx;
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std::vector<Value*> WorkList;
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for (User *AllocaUser : Alloca->users()) {
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GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(AllocaUser);
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if (!GEP) {
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WorkList.push_back(AllocaUser);
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continue;
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}
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Value *Index = GEPToVectorIndex(GEP);
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// If we can't compute a vector index from this GEP, then we can't
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// promote this alloca to vector.
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if (!Index) {
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DEBUG(dbgs() << " Cannot compute vector index for GEP " << *GEP << "\n");
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return false;
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}
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GEPVectorIdx[GEP] = Index;
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for (User *GEPUser : AllocaUser->users()) {
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WorkList.push_back(GEPUser);
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}
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}
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VectorType *VectorTy = arrayTypeToVecType(AllocaTy);
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DEBUG(dbgs() << " Converting alloca to vector "; AllocaTy->dump();
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dbgs() << " -> "; VectorTy->dump(); dbgs() << "\n");
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for (std::vector<Value*>::iterator I = WorkList.begin(),
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E = WorkList.end(); I != E; ++I) {
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Instruction *Inst = cast<Instruction>(*I);
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IRBuilder<> Builder(Inst);
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switch (Inst->getOpcode()) {
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case Instruction::Load: {
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Value *Ptr = Inst->getOperand(0);
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Value *Index = calculateVectorIndex(Ptr, GEPVectorIdx);
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Value *BitCast = Builder.CreateBitCast(Alloca, VectorTy->getPointerTo(0));
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Value *VecValue = Builder.CreateLoad(BitCast);
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Value *ExtractElement = Builder.CreateExtractElement(VecValue, Index);
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Inst->replaceAllUsesWith(ExtractElement);
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Inst->eraseFromParent();
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break;
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}
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case Instruction::Store: {
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Value *Ptr = Inst->getOperand(1);
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Value *Index = calculateVectorIndex(Ptr, GEPVectorIdx);
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Value *BitCast = Builder.CreateBitCast(Alloca, VectorTy->getPointerTo(0));
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Value *VecValue = Builder.CreateLoad(BitCast);
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Value *NewVecValue = Builder.CreateInsertElement(VecValue,
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Inst->getOperand(0),
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Index);
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Builder.CreateStore(NewVecValue, BitCast);
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Inst->eraseFromParent();
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break;
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}
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case Instruction::BitCast:
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break;
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default:
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Inst->dump();
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llvm_unreachable("Do not know how to replace this instruction "
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"with vector op");
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}
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}
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return true;
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}
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static void collectUsesWithPtrTypes(Value *Val, std::vector<Value*> &WorkList) {
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for (User *User : Val->users()) {
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if(std::find(WorkList.begin(), WorkList.end(), User) != WorkList.end())
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continue;
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if (isa<CallInst>(User)) {
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WorkList.push_back(User);
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continue;
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}
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if (!User->getType()->isPointerTy())
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continue;
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WorkList.push_back(User);
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collectUsesWithPtrTypes(User, WorkList);
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}
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}
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void AMDGPUPromoteAlloca::visitAlloca(AllocaInst &I) {
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IRBuilder<> Builder(&I);
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// First try to replace the alloca with a vector
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Type *AllocaTy = I.getAllocatedType();
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DEBUG(dbgs() << "Trying to promote " << I);
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if (tryPromoteAllocaToVector(&I))
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return;
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DEBUG(dbgs() << " alloca is not a candidate for vectorization.\n");
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// FIXME: This is the maximum work group size. We should try to get
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// value from the reqd_work_group_size function attribute if it is
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// available.
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unsigned WorkGroupSize = 256;
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int AllocaSize = WorkGroupSize *
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Mod->getDataLayout()->getTypeAllocSize(AllocaTy);
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if (AllocaSize > LocalMemAvailable) {
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DEBUG(dbgs() << " Not enough local memory to promote alloca.\n");
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return;
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}
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DEBUG(dbgs() << "Promoting alloca to local memory\n");
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LocalMemAvailable -= AllocaSize;
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GlobalVariable *GV = new GlobalVariable(
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*Mod, ArrayType::get(I.getAllocatedType(), 256), false,
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GlobalValue::ExternalLinkage, 0, I.getName(), 0,
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GlobalVariable::NotThreadLocal, AMDGPUAS::LOCAL_ADDRESS);
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FunctionType *FTy = FunctionType::get(
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Type::getInt32Ty(Mod->getContext()), false);
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AttributeSet AttrSet;
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AttrSet.addAttribute(Mod->getContext(), 0, Attribute::ReadNone);
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Value *ReadLocalSizeY = Mod->getOrInsertFunction(
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"llvm.r600.read.local.size.y", FTy, AttrSet);
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Value *ReadLocalSizeZ = Mod->getOrInsertFunction(
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"llvm.r600.read.local.size.z", FTy, AttrSet);
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Value *ReadTIDIGX = Mod->getOrInsertFunction(
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"llvm.r600.read.tidig.x", FTy, AttrSet);
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Value *ReadTIDIGY = Mod->getOrInsertFunction(
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"llvm.r600.read.tidig.y", FTy, AttrSet);
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Value *ReadTIDIGZ = Mod->getOrInsertFunction(
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"llvm.r600.read.tidig.z", FTy, AttrSet);
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Value *TCntY = Builder.CreateCall(ReadLocalSizeY);
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Value *TCntZ = Builder.CreateCall(ReadLocalSizeZ);
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Value *TIdX = Builder.CreateCall(ReadTIDIGX);
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Value *TIdY = Builder.CreateCall(ReadTIDIGY);
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Value *TIdZ = Builder.CreateCall(ReadTIDIGZ);
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Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ);
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Tmp0 = Builder.CreateMul(Tmp0, TIdX);
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Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ);
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Value *TID = Builder.CreateAdd(Tmp0, Tmp1);
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TID = Builder.CreateAdd(TID, TIdZ);
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std::vector<Value*> Indices;
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Indices.push_back(Constant::getNullValue(Type::getInt32Ty(Mod->getContext())));
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Indices.push_back(TID);
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Value *Offset = Builder.CreateGEP(GV, Indices);
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I.mutateType(Offset->getType());
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I.replaceAllUsesWith(Offset);
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I.eraseFromParent();
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std::vector<Value*> WorkList;
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collectUsesWithPtrTypes(Offset, WorkList);
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for (std::vector<Value*>::iterator i = WorkList.begin(),
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e = WorkList.end(); i != e; ++i) {
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Value *V = *i;
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CallInst *Call = dyn_cast<CallInst>(V);
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if (!Call) {
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Type *EltTy = V->getType()->getPointerElementType();
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PointerType *NewTy = PointerType::get(EltTy, AMDGPUAS::LOCAL_ADDRESS);
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V->mutateType(NewTy);
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continue;
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}
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IntrinsicInst *Intr = dyn_cast<IntrinsicInst>(Call);
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if (!Intr) {
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std::vector<Type*> ArgTypes;
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for (unsigned ArgIdx = 0, ArgEnd = Call->getNumArgOperands();
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ArgIdx != ArgEnd; ++ArgIdx) {
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ArgTypes.push_back(Call->getArgOperand(ArgIdx)->getType());
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}
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Function *F = Call->getCalledFunction();
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FunctionType *NewType = FunctionType::get(Call->getType(), ArgTypes,
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F->isVarArg());
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Constant *C = Mod->getOrInsertFunction(StringRef(F->getName().str() + ".local"), NewType,
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F->getAttributes());
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Function *NewF = cast<Function>(C);
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Call->setCalledFunction(NewF);
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continue;
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}
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Builder.SetInsertPoint(Intr);
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switch (Intr->getIntrinsicID()) {
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case Intrinsic::lifetime_start:
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case Intrinsic::lifetime_end:
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// These intrinsics are for address space 0 only
|
||||
Intr->eraseFromParent();
|
||||
continue;
|
||||
case Intrinsic::memcpy: {
|
||||
MemCpyInst *MemCpy = cast<MemCpyInst>(Intr);
|
||||
Builder.CreateMemCpy(MemCpy->getRawDest(), MemCpy->getRawSource(),
|
||||
MemCpy->getLength(), MemCpy->getAlignment(),
|
||||
MemCpy->isVolatile());
|
||||
Intr->eraseFromParent();
|
||||
continue;
|
||||
}
|
||||
case Intrinsic::memset: {
|
||||
MemSetInst *MemSet = cast<MemSetInst>(Intr);
|
||||
Builder.CreateMemSet(MemSet->getRawDest(), MemSet->getValue(),
|
||||
MemSet->getLength(), MemSet->getAlignment(),
|
||||
MemSet->isVolatile());
|
||||
Intr->eraseFromParent();
|
||||
continue;
|
||||
}
|
||||
default:
|
||||
Intr->dump();
|
||||
llvm_unreachable("Don't know how to promote alloca intrinsic use.");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
FunctionPass *llvm::createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST) {
|
||||
return new AMDGPUPromoteAlloca(ST);
|
||||
}
|
||||
@ -41,6 +41,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
|
||||
EnableIfCvt = true;
|
||||
WavefrontSize = 0;
|
||||
CFALUBug = false;
|
||||
LocalMemorySize = 0;
|
||||
ParseSubtargetFeatures(GPU, FS);
|
||||
DevName = GPU;
|
||||
|
||||
@ -109,6 +110,10 @@ AMDGPUSubtarget::hasCFAluBug() const {
|
||||
assert(getGeneration() <= NORTHERN_ISLANDS);
|
||||
return CFALUBug;
|
||||
}
|
||||
int
|
||||
AMDGPUSubtarget::getLocalMemorySize() const {
|
||||
return LocalMemorySize;
|
||||
}
|
||||
bool
|
||||
AMDGPUSubtarget::isTargetELF() const {
|
||||
return false;
|
||||
|
||||
@ -56,6 +56,7 @@ private:
|
||||
bool EnableIfCvt;
|
||||
unsigned WavefrontSize;
|
||||
bool CFALUBug;
|
||||
int LocalMemorySize;
|
||||
|
||||
InstrItineraryData InstrItins;
|
||||
|
||||
@ -109,6 +110,7 @@ public:
|
||||
unsigned getWavefrontSize() const;
|
||||
unsigned getStackEntrySize() const;
|
||||
bool hasCFAluBug() const;
|
||||
int getLocalMemorySize() const;
|
||||
|
||||
bool enableMachineScheduler() const override {
|
||||
return getGeneration() <= NORTHERN_ISLANDS;
|
||||
|
||||
@ -109,6 +109,7 @@ public:
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
virtual void addCodeGenPrepare();
|
||||
bool addPreISel() override;
|
||||
bool addInstSelector() override;
|
||||
bool addPreRegAlloc() override;
|
||||
@ -134,6 +135,13 @@ void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
|
||||
PM.add(createAMDGPUTargetTransformInfoPass(this));
|
||||
}
|
||||
|
||||
void AMDGPUPassConfig::addCodeGenPrepare() {
|
||||
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
|
||||
addPass(createAMDGPUPromoteAlloca(ST));
|
||||
addPass(createSROAPass());
|
||||
TargetPassConfig::addCodeGenPrepare();
|
||||
}
|
||||
|
||||
bool
|
||||
AMDGPUPassConfig::addPreISel() {
|
||||
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
|
||||
|
||||
@ -25,6 +25,7 @@ add_llvm_target(R600CodeGen
|
||||
AMDGPUTargetTransformInfo.cpp
|
||||
AMDGPUISelLowering.cpp
|
||||
AMDGPUInstrInfo.cpp
|
||||
AMDGPUPromoteAlloca.cpp
|
||||
AMDGPURegisterInfo.cpp
|
||||
R600ClauseMergePass.cpp
|
||||
R600ControlFlowFinalizer.cpp
|
||||
|
||||
@ -136,6 +136,16 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
|
||||
setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
|
||||
setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
|
||||
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
|
||||
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
|
||||
|
||||
setTargetDAGCombine(ISD::FP_ROUND);
|
||||
setTargetDAGCombine(ISD::FP_TO_SINT);
|
||||
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
|
||||
@ -540,6 +550,8 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
||||
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
|
||||
switch (Op.getOpcode()) {
|
||||
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
|
||||
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
|
||||
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
|
||||
case ISD::FCOS:
|
||||
case ISD::FSIN: return LowerTrig(Op, DAG);
|
||||
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
||||
@ -812,6 +824,56 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
|
||||
}
|
||||
}
|
||||
|
||||
SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
|
||||
SDValue Vector) const {
|
||||
|
||||
SDLoc DL(Vector);
|
||||
EVT VecVT = Vector.getValueType();
|
||||
EVT EltVT = VecVT.getVectorElementType();
|
||||
SmallVector<SDValue, 8> Args;
|
||||
|
||||
for (unsigned i = 0, e = VecVT.getVectorNumElements();
|
||||
i != e; ++i) {
|
||||
Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
|
||||
Vector, DAG.getConstant(i, getVectorIdxTy())));
|
||||
}
|
||||
|
||||
return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
|
||||
}
|
||||
|
||||
SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
|
||||
SDLoc DL(Op);
|
||||
SDValue Vector = Op.getOperand(0);
|
||||
SDValue Index = Op.getOperand(1);
|
||||
|
||||
if (isa<ConstantSDNode>(Index) ||
|
||||
Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
|
||||
return Op;
|
||||
|
||||
Vector = vectorToVerticalVector(DAG, Vector);
|
||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
|
||||
Vector, Index);
|
||||
}
|
||||
|
||||
SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
SDLoc DL(Op);
|
||||
SDValue Vector = Op.getOperand(0);
|
||||
SDValue Value = Op.getOperand(1);
|
||||
SDValue Index = Op.getOperand(2);
|
||||
|
||||
if (isa<ConstantSDNode>(Index) ||
|
||||
Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
|
||||
return Op;
|
||||
|
||||
Vector = vectorToVerticalVector(DAG, Vector);
|
||||
SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
|
||||
Vector, Value, Index);
|
||||
return vectorToVerticalVector(DAG, Insert);
|
||||
}
|
||||
|
||||
SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
|
||||
// On hw >= R700, COS/SIN input must be between -1. and 1.
|
||||
// Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
|
||||
|
||||
@ -51,7 +51,10 @@ private:
|
||||
void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
|
||||
MachineRegisterInfo & MRI, unsigned dword_offset) const;
|
||||
SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
|
||||
SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
|
||||
|
||||
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
@ -51,11 +51,15 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
bool KillSrc) const {
|
||||
unsigned VectorComponents = 0;
|
||||
if (AMDGPU::R600_Reg128RegClass.contains(DestReg) &&
|
||||
AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
|
||||
if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) ||
|
||||
AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) &&
|
||||
(AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
|
||||
AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
|
||||
VectorComponents = 4;
|
||||
} else if(AMDGPU::R600_Reg64RegClass.contains(DestReg) &&
|
||||
AMDGPU::R600_Reg64RegClass.contains(SrcReg)) {
|
||||
} else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) ||
|
||||
AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) &&
|
||||
(AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
|
||||
AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
|
||||
VectorComponents = 2;
|
||||
}
|
||||
|
||||
@ -1053,6 +1057,29 @@ unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
||||
return 2;
|
||||
}
|
||||
|
||||
bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
|
||||
|
||||
switch(MI->getOpcode()) {
|
||||
default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
|
||||
case AMDGPU::R600_EXTRACT_ELT_V2:
|
||||
case AMDGPU::R600_EXTRACT_ELT_V4:
|
||||
buildIndirectRead(MI->getParent(), MI, MI->getOperand(0).getReg(),
|
||||
RI.getHWRegIndex(MI->getOperand(1).getReg()), // Address
|
||||
MI->getOperand(2).getReg(),
|
||||
RI.getHWRegChan(MI->getOperand(1).getReg()));
|
||||
break;
|
||||
case AMDGPU::R600_INSERT_ELT_V2:
|
||||
case AMDGPU::R600_INSERT_ELT_V4:
|
||||
buildIndirectWrite(MI->getParent(), MI, MI->getOperand(2).getReg(), // Value
|
||||
RI.getHWRegIndex(MI->getOperand(1).getReg()), // Address
|
||||
MI->getOperand(3).getReg(), // Offset
|
||||
RI.getHWRegChan(MI->getOperand(1).getReg())); // Channel
|
||||
break;
|
||||
}
|
||||
MI->eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
|
||||
const MachineFunction &MF) const {
|
||||
const AMDGPUFrameLowering *TFL =
|
||||
@ -1090,7 +1117,22 @@ MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg) const {
|
||||
unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
|
||||
return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
|
||||
}
|
||||
|
||||
MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg,
|
||||
unsigned AddrChan) const {
|
||||
unsigned AddrReg;
|
||||
switch (AddrChan) {
|
||||
default: llvm_unreachable("Invalid Channel");
|
||||
case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
|
||||
case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
|
||||
case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
|
||||
case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
|
||||
}
|
||||
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
|
||||
AMDGPU::AR_X, OffsetReg);
|
||||
setImmOperand(MOVA, AMDGPU::OpName::write, 0);
|
||||
@ -1107,7 +1149,22 @@ MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg) const {
|
||||
unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
|
||||
return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
|
||||
}
|
||||
|
||||
MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg,
|
||||
unsigned AddrChan) const {
|
||||
unsigned AddrReg;
|
||||
switch (AddrChan) {
|
||||
default: llvm_unreachable("Invalid Channel");
|
||||
case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break;
|
||||
case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break;
|
||||
case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break;
|
||||
case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break;
|
||||
}
|
||||
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
|
||||
AMDGPU::AR_X,
|
||||
OffsetReg);
|
||||
|
||||
@ -36,6 +36,18 @@ namespace llvm {
|
||||
std::vector<std::pair<int, unsigned> >
|
||||
ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
|
||||
|
||||
|
||||
MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg,
|
||||
unsigned AddrChan) const;
|
||||
|
||||
MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
unsigned ValueReg, unsigned Address,
|
||||
unsigned OffsetReg,
|
||||
unsigned AddrChan) const;
|
||||
public:
|
||||
enum BankSwizzle {
|
||||
ALU_VEC_012_SCL_210 = 0,
|
||||
@ -195,6 +207,8 @@ namespace llvm {
|
||||
int getInstrLatency(const InstrItineraryData *ItinData,
|
||||
SDNode *Node) const override { return 1;}
|
||||
|
||||
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
|
||||
|
||||
/// \brief Reserve the registers that may be accesed using indirect addressing.
|
||||
void reserveIndirectRegisters(BitVector &Reserved,
|
||||
const MachineFunction &MF) const;
|
||||
|
||||
@ -1581,6 +1581,60 @@ let isTerminator=1 in {
|
||||
defm CONTINUEC : BranchInstr2<"CONTINUEC">;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Indirect addressing pseudo instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isPseudo = 1 in {
|
||||
|
||||
class ExtractVertical <RegisterClass vec_rc> : InstR600 <
|
||||
(outs R600_Reg32:$dst),
|
||||
(ins vec_rc:$vec, R600_Reg32:$index), "",
|
||||
[],
|
||||
AnyALU
|
||||
>;
|
||||
|
||||
let Constraints = "$dst = $vec" in {
|
||||
|
||||
class InsertVertical <RegisterClass vec_rc> : InstR600 <
|
||||
(outs vec_rc:$dst),
|
||||
(ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "",
|
||||
[],
|
||||
AnyALU
|
||||
>;
|
||||
|
||||
} // End Constraints = "$dst = $vec"
|
||||
|
||||
} // End isPseudo = 1
|
||||
|
||||
def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>;
|
||||
def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>;
|
||||
|
||||
def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>;
|
||||
def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>;
|
||||
|
||||
class ExtractVerticalPat <Instruction inst, ValueType vec_ty,
|
||||
ValueType scalar_ty> : Pat <
|
||||
(scalar_ty (extractelt vec_ty:$vec, i32:$index)),
|
||||
(inst $vec, $index)
|
||||
>;
|
||||
|
||||
def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>;
|
||||
def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
|
||||
def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>;
|
||||
def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
|
||||
|
||||
class InsertVerticalPat <Instruction inst, ValueType vec_ty,
|
||||
ValueType scalar_ty> : Pat <
|
||||
(vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)),
|
||||
(inst $vec, $value, $index)
|
||||
>;
|
||||
|
||||
def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>;
|
||||
def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
|
||||
def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>;
|
||||
def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ISel Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -18,18 +18,28 @@ class R600RegWithChan <string name, bits<9> sel, string chan> :
|
||||
|
||||
class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
|
||||
RegisterWithSubRegs<n, subregs> {
|
||||
field bits<2> chan_encoding = 0;
|
||||
let Namespace = "AMDGPU";
|
||||
let SubRegIndices = [sub0, sub1, sub2, sub3];
|
||||
let HWEncoding = encoding;
|
||||
let HWEncoding{8-0} = encoding{8-0};
|
||||
let HWEncoding{10-9} = chan_encoding;
|
||||
}
|
||||
|
||||
class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
|
||||
RegisterWithSubRegs<n, subregs> {
|
||||
field bits<2> chan_encoding = 0;
|
||||
let Namespace = "AMDGPU";
|
||||
let SubRegIndices = [sub0, sub1];
|
||||
let HWEncoding = encoding;
|
||||
let HWEncoding{8-0} = encoding{8-0};
|
||||
let HWEncoding{10-9} = chan_encoding;
|
||||
}
|
||||
|
||||
class R600Reg_64Vertical<int lo, int hi, string chan> : R600Reg_64 <
|
||||
"V"#lo#hi#"_"#chan,
|
||||
[!cast<Register>("T"#lo#"_"#chan), !cast<Register>("T"#hi#"_"#chan)],
|
||||
lo
|
||||
>;
|
||||
|
||||
foreach Index = 0-127 in {
|
||||
foreach Chan = [ "X", "Y", "Z", "W" ] in {
|
||||
@ -54,6 +64,24 @@ foreach Index = 0-127 in {
|
||||
Index>;
|
||||
}
|
||||
|
||||
foreach Chan = [ "X", "Y", "Z", "W"] in {
|
||||
|
||||
let chan_encoding = !if(!eq(Chan, "X"), 0,
|
||||
!if(!eq(Chan, "Y"), 1,
|
||||
!if(!eq(Chan, "Z"), 2,
|
||||
!if(!eq(Chan, "W"), 3, 0)))) in {
|
||||
def V0123_#Chan : R600Reg_128 <"V0123_"#Chan,
|
||||
[!cast<Register>("T0_"#Chan),
|
||||
!cast<Register>("T1_"#Chan),
|
||||
!cast<Register>("T2_"#Chan),
|
||||
!cast<Register>("T3_"#Chan)],
|
||||
0>;
|
||||
def V01_#Chan : R600Reg_64Vertical<0, 1, Chan>;
|
||||
def V23_#Chan : R600Reg_64Vertical<2, 3, Chan>;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// KCACHE_BANK0
|
||||
foreach Index = 159-128 in {
|
||||
foreach Chan = [ "X", "Y", "Z", "W" ] in {
|
||||
@ -130,8 +158,14 @@ def ALU_PARAM : R600Reg<"Param", 0>;
|
||||
|
||||
let isAllocatable = 0 in {
|
||||
|
||||
// XXX: Only use the X channel, until we support wider stack widths
|
||||
def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
|
||||
def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
|
||||
|
||||
// We only use Addr_[YZW] for vertical vectors.
|
||||
// FIXME if we add more vertical vector registers we will need to ad more
|
||||
// registers to these classes.
|
||||
def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;
|
||||
def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;
|
||||
def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;
|
||||
|
||||
def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
|
||||
(add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>;
|
||||
@ -206,5 +240,13 @@ def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
|
||||
let CopyCost = -1;
|
||||
}
|
||||
|
||||
def R600_Reg128Vertical : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
|
||||
(add V0123_W, V0123_Z, V0123_Y, V0123_X)
|
||||
>;
|
||||
|
||||
def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
|
||||
(add (sequence "T%u_XY", 0, 63))>;
|
||||
|
||||
def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
|
||||
(add V01_X, V01_Y, V01_Z, V01_W,
|
||||
V23_X, V23_Y, V23_Z, V23_W)>;
|
||||
|
||||
@ -2560,13 +2560,13 @@ multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST I
|
||||
// 1. Extract with offset
|
||||
def : Pat<
|
||||
(vector_extract vt:$vec, (add i32:$idx, imm:$off)),
|
||||
(f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
|
||||
(eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
|
||||
>;
|
||||
|
||||
// 2. Extract without offset
|
||||
def : Pat<
|
||||
(vector_extract vt:$vec, i32:$idx),
|
||||
(f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
|
||||
(eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
|
||||
>;
|
||||
|
||||
// 3. Insert with offset
|
||||
|
||||
@ -10,7 +10,12 @@ declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
|
||||
|
||||
; SI-LABEL: @test_private_array_ptr_calc:
|
||||
; SI: V_ADD_I32_e32 [[PTRREG:v[0-9]+]]
|
||||
; SI: V_MOVRELD_B32_e32 {{v[0-9]+}}, [[PTRREG]]
|
||||
;
|
||||
; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
|
||||
; alloca to a vector. It currently fails because it does not know how
|
||||
; to interpret:
|
||||
; getelementptr [4 x i32]* %alloca, i32 1, i32 %b
|
||||
; SI: DS_WRITE_B32 {{v[0-9]+}}, [[PTRREG]]
|
||||
define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
|
||||
%alloca = alloca [4 x i32], i32 4, align 16
|
||||
%tid = call i32 @llvm.SI.tid() readnone
|
||||
|
||||
@ -3,10 +3,8 @@
|
||||
declare void @llvm.AMDGPU.barrier.local() noduplicate nounwind
|
||||
|
||||
; SI-LABEL: @private_access_f64_alloca:
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_READ_B64
|
||||
define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind {
|
||||
%val = load double addrspace(1)* %in, align 8
|
||||
%array = alloca double, i32 16, align 8
|
||||
@ -19,14 +17,10 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double
|
||||
}
|
||||
|
||||
; SI-LABEL: @private_access_v2f64_alloca:
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_READ_B64
|
||||
; SI: DS_READ_B64
|
||||
define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind {
|
||||
%val = load <2 x double> addrspace(1)* %in, align 16
|
||||
%array = alloca <2 x double>, i32 16, align 16
|
||||
@ -39,10 +33,8 @@ define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out
|
||||
}
|
||||
|
||||
; SI-LABEL: @private_access_i64_alloca:
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_READ_B64
|
||||
define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind {
|
||||
%val = load i64 addrspace(1)* %in, align 8
|
||||
%array = alloca i64, i32 16, align 8
|
||||
@ -55,14 +47,10 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs
|
||||
}
|
||||
|
||||
; SI-LABEL: @private_access_v2i64_alloca:
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELD_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: V_MOVRELS_B32_e32
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_WRITE_B64
|
||||
; SI: DS_READ_B64
|
||||
; SI: DS_READ_B64
|
||||
define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind {
|
||||
%val = load <2 x i64> addrspace(1)* %in, align 16
|
||||
%array = alloca <2 x i64>, i32 16, align 16
|
||||
|
||||
@ -2,10 +2,13 @@
|
||||
; REQUIRES: asserts
|
||||
; RUN: llc -march=r600 -mcpu=SI < %s
|
||||
|
||||
define void @large_alloca(i32 addrspace(1)* %out, i32 %x) nounwind {
|
||||
%large = alloca [256 x i32], align 4
|
||||
%gep = getelementptr [256 x i32]* %large, i32 0, i32 255
|
||||
define void @large_alloca(i32 addrspace(1)* %out, i32 %x, i32 %y) nounwind {
|
||||
%large = alloca [8192 x i32], align 4
|
||||
%gep = getelementptr [8192 x i32]* %large, i32 0, i32 8191
|
||||
store i32 %x, i32* %gep
|
||||
%gep1 = getelementptr [8192 x i32]* %large, i32 0, i32 %y
|
||||
%0 = load i32* %gep1
|
||||
store i32 %0, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
@ -7,6 +7,12 @@
|
||||
; CHECK: AND_INT
|
||||
; CHECK-NEXT: AND_INT
|
||||
; CHECK-NEXT: OR_INT
|
||||
|
||||
; FIXME: For some reason having the allocas here allowed the flatten cfg pass
|
||||
; to do its transfomation, however now that we are using local memory for
|
||||
; allocas, the transformation isn't happening.
|
||||
; XFAIL: *
|
||||
|
||||
define void @_Z9chk1D_512v() #0 {
|
||||
entry:
|
||||
%a0 = alloca i32, align 4
|
||||
|
||||
@ -3,6 +3,11 @@
|
||||
;
|
||||
; CFG flattening should use parallel-or to generate branch conditions and
|
||||
; then merge if-regions with the same bodies.
|
||||
|
||||
; FIXME: For some reason having the allocas here allowed the flatten cfg pass
|
||||
; to do its transfomation, however now that we are using local memory for
|
||||
; allocas, the transformation isn't happening.
|
||||
; XFAIL: *
|
||||
;
|
||||
; CHECK: OR_INT
|
||||
; CHECK-NEXT: OR_INT
|
||||
|
||||
@ -1,24 +1,17 @@
|
||||
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=R600-CHECK --check-prefix=FUNC
|
||||
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
|
||||
|
||||
; This test checks that uses and defs of the AR register happen in the same
|
||||
; instruction clause.
|
||||
|
||||
; FUNC-LABEL: @mova_same_clause
|
||||
|
||||
; R600-CHECK: MOVA_INT
|
||||
; R600-CHECK-NOT: ALU clause
|
||||
; R600-CHECK: 0 + AR.x
|
||||
; R600-CHECK: MOVA_INT
|
||||
; R600-CHECK-NOT: ALU clause
|
||||
; R600-CHECK: 0 + AR.x
|
||||
; R600-CHECK: LDS_WRITE
|
||||
; R600-CHECK: LDS_WRITE
|
||||
; R600-CHECK: LDS_READ
|
||||
; R600-CHECK: LDS_READ
|
||||
|
||||
; SI-CHECK: V_READFIRSTLANE_B32 vcc_lo
|
||||
; SI-CHECK: V_MOVRELD
|
||||
; SI-CHECK: S_CBRANCH
|
||||
; SI-CHECK: V_READFIRSTLANE_B32 vcc_lo
|
||||
; SI-CHECK: V_MOVRELD
|
||||
; SI-CHECK: S_CBRANCH
|
||||
; SI-CHECK: DS_WRITE_B32
|
||||
; SI-CHECK: DS_WRITE_B32
|
||||
; SI-CHECK: DS_READ_B32
|
||||
; SI-CHECK: DS_READ_B32
|
||||
define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
|
||||
entry:
|
||||
%stack = alloca [5 x i32], align 4
|
||||
@ -114,12 +107,8 @@ for.end:
|
||||
|
||||
; FUNC-LABEL: @short_array
|
||||
|
||||
; R600-CHECK: MOV {{\** *}}T{{[0-9]\.[XYZW]}}, literal
|
||||
; R600-CHECK: 65536
|
||||
; R600-CHECK: *
|
||||
; R600-CHECK: MOVA_INT
|
||||
|
||||
; SI-CHECK: V_MOV_B32_e32 v{{[0-9]}}, 0x10000
|
||||
; SI-CHECK: V_MOVRELS_B32_e32
|
||||
define void @short_array(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
@ -137,10 +126,7 @@ entry:
|
||||
|
||||
; FUNC-LABEL: @char_array
|
||||
|
||||
; R600-CHECK: OR_INT {{\** *}}T{{[0-9]\.[XYZW]}}, {{[PVT0-9]+\.[XYZW]}}, literal
|
||||
; R600-CHECK: 256
|
||||
; R600-CHECK: *
|
||||
; R600-CHECK-NEXT: MOVA_INT
|
||||
; R600-CHECK: MOVA_INT
|
||||
|
||||
; SI-CHECK: V_OR_B32_e32 v{{[0-9]}}, 0x100
|
||||
; SI-CHECK: V_MOVRELS_B32_e32
|
||||
@ -185,7 +171,9 @@ entry:
|
||||
; Test that two stack objects are not stored in the same register
|
||||
; The second stack object should be in T3.X
|
||||
; FUNC-LABEL: @no_overlap
|
||||
; R600-CHECK: MOV {{\** *}}T3.X
|
||||
; R600_CHECK: MOV
|
||||
; R600_CHECK: [[CHAN:[XYZW]]]+
|
||||
; R600-CHECK-NOT: [[CHAN]]+
|
||||
; SI-CHECK: V_MOV_B32_e32 v3
|
||||
define void @no_overlap(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
|
||||
|
||||
; XFAIL: *
|
||||
|
||||
; 64-bit select was originally lowered with a build_pair, and this
|
||||
; could be simplified to 1 cndmask instead of 2, but that broken when
|
||||
; it started being implemented with a v2i32 build_vector and
|
||||
@ -12,9 +14,10 @@ define void @trunc_select_i64(i32 addrspace(1)* %out, i64 %a, i64 %b, i32 %c) {
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Fix truncating store for local memory
|
||||
; SI-LABEL: @trunc_load_alloca_i64:
|
||||
; SI: V_MOVRELS_B32
|
||||
; SI-NOT: V_MOVRELS_B32
|
||||
; SI: DS_READ_B32
|
||||
; SI-NOT: DS_READ_B64
|
||||
; SI: S_ENDPGM
|
||||
define void @trunc_load_alloca_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) {
|
||||
%idx = add i32 %a, %b
|
||||
|
||||
74
test/CodeGen/R600/vector-alloca.ll
Normal file
74
test/CodeGen/R600/vector-alloca.ll
Normal file
@ -0,0 +1,74 @@
|
||||
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
|
||||
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
|
||||
|
||||
; FUNC-LABEL: @vector_read
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOVA_INT
|
||||
define void @vector_read(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
%0 = alloca [4 x i32]
|
||||
%x = getelementptr [4 x i32]* %0, i32 0, i32 0
|
||||
%y = getelementptr [4 x i32]* %0, i32 0, i32 1
|
||||
%z = getelementptr [4 x i32]* %0, i32 0, i32 2
|
||||
%w = getelementptr [4 x i32]* %0, i32 0, i32 3
|
||||
store i32 0, i32* %x
|
||||
store i32 1, i32* %y
|
||||
store i32 2, i32* %z
|
||||
store i32 3, i32* %w
|
||||
%1 = getelementptr [4 x i32]* %0, i32 0, i32 %index
|
||||
%2 = load i32* %1
|
||||
store i32 %2, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @vector_write
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOV
|
||||
; EG: MOVA_INT
|
||||
; EG: MOVA_INT
|
||||
define void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
|
||||
entry:
|
||||
%0 = alloca [4 x i32]
|
||||
%x = getelementptr [4 x i32]* %0, i32 0, i32 0
|
||||
%y = getelementptr [4 x i32]* %0, i32 0, i32 1
|
||||
%z = getelementptr [4 x i32]* %0, i32 0, i32 2
|
||||
%w = getelementptr [4 x i32]* %0, i32 0, i32 3
|
||||
store i32 0, i32* %x
|
||||
store i32 0, i32* %y
|
||||
store i32 0, i32* %z
|
||||
store i32 0, i32* %w
|
||||
%1 = getelementptr [4 x i32]* %0, i32 0, i32 %w_index
|
||||
store i32 1, i32* %1
|
||||
%2 = getelementptr [4 x i32]* %0, i32 0, i32 %r_index
|
||||
%3 = load i32* %2
|
||||
store i32 %3, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; This test should be optimize to:
|
||||
; store i32 0, i32 addrspace(1)* %out
|
||||
; FUNC-LABEL: @bitcast_gep
|
||||
; CHECK: STORE_RAW
|
||||
define void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
|
||||
entry:
|
||||
%0 = alloca [4 x i32]
|
||||
%x = getelementptr [4 x i32]* %0, i32 0, i32 0
|
||||
%y = getelementptr [4 x i32]* %0, i32 0, i32 1
|
||||
%z = getelementptr [4 x i32]* %0, i32 0, i32 2
|
||||
%w = getelementptr [4 x i32]* %0, i32 0, i32 3
|
||||
store i32 0, i32* %x
|
||||
store i32 0, i32* %y
|
||||
store i32 0, i32* %z
|
||||
store i32 0, i32* %w
|
||||
%1 = getelementptr [4 x i32]* %0, i32 0, i32 1
|
||||
%2 = bitcast i32* %1 to [4 x i32]*
|
||||
%3 = getelementptr [4 x i32]* %2, i32 0, i32 0
|
||||
%4 = load i32* %3
|
||||
store i32 %4, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user