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[X86] Break non-power of 2 vXi1 vectors into scalars for argument passing with avx512.
This generates worse code, but matches what is done for avx2 and prevents crashes when more arguments are passed than we have registers for. llvm-svn: 372200
This commit is contained in:
Craig Topper
parent
043fb9113b
commit
a5385636e7
@ -1996,14 +1996,16 @@ X86TargetLowering::getPreferredVectorAction(MVT VT) const {
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MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const {
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// Break wide vXi1 vectors into scalars to match avx2 behavior.
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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Subtarget.hasAVX512() &&
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((VT.getVectorNumElements() > 32 && !Subtarget.hasBWI()) ||
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(VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
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return MVT::i8;
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// v32i1 vectors should be promoted to v32i8 to match avx2.
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if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
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return MVT::v32i8;
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// Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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Subtarget.hasAVX512() &&
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(!isPowerOf2_32(VT.getVectorNumElements()) ||
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(VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
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(VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
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return MVT::i8;
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// FIXME: Should we just make these types legal and custom split operations?
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if ((VT == MVT::v32i16 || VT == MVT::v64i8) &&
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Subtarget.hasAVX512() && !Subtarget.hasBWI() && !EnableOldKNLABI)
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@ -2014,14 +2016,16 @@ MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
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unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const {
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// Break wide vXi1 vectors into scalars to match avx2 behavior.
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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Subtarget.hasAVX512() &&
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((VT.getVectorNumElements() > 32 && !Subtarget.hasBWI()) ||
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(VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
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return VT.getVectorNumElements();
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// v32i1 vectors should be promoted to v32i8 to match avx2.
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if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
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return 1;
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// Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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Subtarget.hasAVX512() &&
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(!isPowerOf2_32(VT.getVectorNumElements()) ||
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(VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
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(VT.getVectorNumElements() > 64 && Subtarget.hasBWI())))
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return VT.getVectorNumElements();
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// FIXME: Should we just make these types legal and custom split operations?
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if ((VT == MVT::v32i16 || VT == MVT::v64i8) &&
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Subtarget.hasAVX512() && !Subtarget.hasBWI() && !EnableOldKNLABI)
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@ -2032,10 +2036,11 @@ unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
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unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
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LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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unsigned &NumIntermediates, MVT &RegisterVT) const {
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// Break wide vXi1 vectors into scalars to match avx2 behavior.
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// Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1 &&
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Subtarget.hasAVX512() &&
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((VT.getVectorNumElements() > 32 && !Subtarget.hasBWI()) ||
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(!isPowerOf2_32(VT.getVectorNumElements()) ||
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(VT.getVectorNumElements() > 16 && !Subtarget.hasBWI()) ||
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(VT.getVectorNumElements() > 64 && Subtarget.hasBWI()))) {
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RegisterVT = MVT::i8;
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IntermediateVT = MVT::i1;
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File diff suppressed because it is too large
Load Diff
@ -1626,75 +1626,62 @@ declare <3 x i32> @llvm.masked.gather.v3i32.v3p0i32(<3 x i32*>, i32, <3 x i1>, <
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define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x i32> %src0) {
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; KNL_64-LABEL: test30:
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; KNL_64: # %bb.0:
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; KNL_64-NEXT: vpslld $31, %xmm2, %xmm2
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; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k0
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; KNL_64-NEXT: kshiftrw $1, %k0, %k1
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; KNL_64-NEXT: kshiftrw $2, %k0, %k2
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; KNL_64-NEXT: kmovw %k0, %eax
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; KNL_64-NEXT: andb $1, %al
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; KNL_64-NEXT: kmovw %k1, %ecx
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; KNL_64-NEXT: andb $1, %cl
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; KNL_64-NEXT: addb %cl, %cl
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; KNL_64-NEXT: orb %al, %cl
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; KNL_64-NEXT: kmovw %k2, %eax
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; KNL_64-NEXT: andb $1, %al
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; KNL_64-NEXT: shlb $2, %al
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; KNL_64-NEXT: orb %cl, %al
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; KNL_64-NEXT: andb $1, %dil
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; KNL_64-NEXT: andb $1, %sil
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; KNL_64-NEXT: addb %sil, %sil
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; KNL_64-NEXT: orb %dil, %sil
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; KNL_64-NEXT: andb $1, %dl
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; KNL_64-NEXT: shlb $2, %dl
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; KNL_64-NEXT: orb %sil, %dl
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; KNL_64-NEXT: vpmovsxdq %xmm1, %ymm1
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; KNL_64-NEXT: vpsllq $2, %ymm1, %ymm1
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; KNL_64-NEXT: vpaddq %ymm1, %ymm0, %ymm0
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; KNL_64-NEXT: testb $1, %al
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; KNL_64-NEXT: testb $1, %dl
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; KNL_64-NEXT: jne .LBB31_1
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; KNL_64-NEXT: # %bb.2: # %else
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; KNL_64-NEXT: testb $2, %al
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; KNL_64-NEXT: testb $2, %dl
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; KNL_64-NEXT: jne .LBB31_3
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; KNL_64-NEXT: .LBB31_4: # %else2
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; KNL_64-NEXT: testb $4, %al
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; KNL_64-NEXT: testb $4, %dl
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; KNL_64-NEXT: jne .LBB31_5
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; KNL_64-NEXT: .LBB31_6: # %else5
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; KNL_64-NEXT: vmovdqa %xmm3, %xmm0
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; KNL_64-NEXT: vmovdqa %xmm2, %xmm0
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; KNL_64-NEXT: vzeroupper
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; KNL_64-NEXT: retq
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; KNL_64-NEXT: .LBB31_1: # %cond.load
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; KNL_64-NEXT: vmovq %xmm0, %rcx
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; KNL_64-NEXT: vpinsrd $0, (%rcx), %xmm3, %xmm3
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; KNL_64-NEXT: testb $2, %al
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; KNL_64-NEXT: vmovq %xmm0, %rax
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; KNL_64-NEXT: vpinsrd $0, (%rax), %xmm2, %xmm2
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; KNL_64-NEXT: testb $2, %dl
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; KNL_64-NEXT: je .LBB31_4
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; KNL_64-NEXT: .LBB31_3: # %cond.load1
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; KNL_64-NEXT: vpextrq $1, %xmm0, %rcx
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; KNL_64-NEXT: vpinsrd $1, (%rcx), %xmm3, %xmm3
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; KNL_64-NEXT: testb $4, %al
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; KNL_64-NEXT: vpextrq $1, %xmm0, %rax
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; KNL_64-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2
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; KNL_64-NEXT: testb $4, %dl
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; KNL_64-NEXT: je .LBB31_6
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; KNL_64-NEXT: .LBB31_5: # %cond.load4
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; KNL_64-NEXT: vextracti128 $1, %ymm0, %xmm0
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; KNL_64-NEXT: vmovq %xmm0, %rax
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; KNL_64-NEXT: vpinsrd $2, (%rax), %xmm3, %xmm3
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; KNL_64-NEXT: vmovdqa %xmm3, %xmm0
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; KNL_64-NEXT: vpinsrd $2, (%rax), %xmm2, %xmm2
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; KNL_64-NEXT: vmovdqa %xmm2, %xmm0
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; KNL_64-NEXT: vzeroupper
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; KNL_64-NEXT: retq
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;
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; KNL_32-LABEL: test30:
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; KNL_32: # %bb.0:
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; KNL_32-NEXT: subl $12, %esp
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; KNL_32-NEXT: .cfi_def_cfa_offset 16
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; KNL_32-NEXT: vmovdqa %xmm0, %xmm3
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; KNL_32-NEXT: vpslld $31, %xmm2, %xmm0
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; KNL_32-NEXT: vptestmd %zmm0, %zmm0, %k0
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; KNL_32-NEXT: kshiftrw $1, %k0, %k1
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; KNL_32-NEXT: kshiftrw $2, %k0, %k2
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; KNL_32-NEXT: kmovw %k0, %eax
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; KNL_32-NEXT: pushl %eax
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; KNL_32-NEXT: .cfi_def_cfa_offset 8
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; KNL_32-NEXT: movb {{[0-9]+}}(%esp), %al
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; KNL_32-NEXT: andb $1, %al
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; KNL_32-NEXT: kmovw %k1, %ecx
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; KNL_32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; KNL_32-NEXT: andb $1, %cl
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; KNL_32-NEXT: addb %cl, %cl
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; KNL_32-NEXT: orb %al, %cl
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; KNL_32-NEXT: kmovw %k2, %eax
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; KNL_32-NEXT: movb {{[0-9]+}}(%esp), %al
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; KNL_32-NEXT: andb $1, %al
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; KNL_32-NEXT: shlb $2, %al
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; KNL_32-NEXT: orb %cl, %al
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; KNL_32-NEXT: vmovdqa {{[0-9]+}}(%esp), %xmm0
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; KNL_32-NEXT: vpslld $2, %xmm1, %xmm1
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; KNL_32-NEXT: vpaddd %xmm1, %xmm3, %xmm1
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; KNL_32-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; KNL_32-NEXT: testb $1, %al
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; KNL_32-NEXT: jne .LBB31_1
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; KNL_32-NEXT: # %bb.2: # %else
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@ -1702,102 +1689,86 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x
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; KNL_32-NEXT: jne .LBB31_3
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; KNL_32-NEXT: .LBB31_4: # %else2
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; KNL_32-NEXT: testb $4, %al
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; KNL_32-NEXT: jne .LBB31_5
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; KNL_32-NEXT: je .LBB31_6
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; KNL_32-NEXT: .LBB31_5: # %cond.load4
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; KNL_32-NEXT: vpextrd $2, %xmm0, %eax
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; KNL_32-NEXT: vpinsrd $2, (%eax), %xmm2, %xmm2
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; KNL_32-NEXT: .LBB31_6: # %else5
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; KNL_32-NEXT: addl $12, %esp
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; KNL_32-NEXT: vmovdqa %xmm2, %xmm0
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; KNL_32-NEXT: popl %eax
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; KNL_32-NEXT: .cfi_def_cfa_offset 4
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; KNL_32-NEXT: vzeroupper
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; KNL_32-NEXT: retl
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; KNL_32-NEXT: .LBB31_1: # %cond.load
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; KNL_32-NEXT: .cfi_def_cfa_offset 16
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; KNL_32-NEXT: vmovd %xmm1, %ecx
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; KNL_32-NEXT: vpinsrd $0, (%ecx), %xmm0, %xmm0
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; KNL_32-NEXT: .cfi_def_cfa_offset 8
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; KNL_32-NEXT: vmovd %xmm0, %ecx
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; KNL_32-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2
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; KNL_32-NEXT: testb $2, %al
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; KNL_32-NEXT: je .LBB31_4
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; KNL_32-NEXT: .LBB31_3: # %cond.load1
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; KNL_32-NEXT: vpextrd $1, %xmm1, %ecx
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; KNL_32-NEXT: vpinsrd $1, (%ecx), %xmm0, %xmm0
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; KNL_32-NEXT: vpextrd $1, %xmm0, %ecx
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; KNL_32-NEXT: vpinsrd $1, (%ecx), %xmm2, %xmm2
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; KNL_32-NEXT: testb $4, %al
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; KNL_32-NEXT: je .LBB31_6
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; KNL_32-NEXT: .LBB31_5: # %cond.load4
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; KNL_32-NEXT: vpextrd $2, %xmm1, %eax
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; KNL_32-NEXT: vpinsrd $2, (%eax), %xmm0, %xmm0
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; KNL_32-NEXT: addl $12, %esp
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; KNL_32-NEXT: .cfi_def_cfa_offset 4
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; KNL_32-NEXT: vzeroupper
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; KNL_32-NEXT: retl
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; KNL_32-NEXT: jne .LBB31_5
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; KNL_32-NEXT: jmp .LBB31_6
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;
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; SKX-LABEL: test30:
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; SKX: # %bb.0:
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; SKX-NEXT: vpslld $31, %xmm2, %xmm2
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; SKX-NEXT: vpmovd2m %xmm2, %k0
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; SKX-NEXT: kshiftrb $1, %k0, %k1
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; SKX-NEXT: kshiftrb $2, %k0, %k2
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; SKX-NEXT: kmovw %k0, %eax
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; SKX-NEXT: andb $1, %al
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; SKX-NEXT: kmovw %k1, %ecx
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; SKX-NEXT: andb $1, %cl
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; SKX-NEXT: addb %cl, %cl
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; SKX-NEXT: orb %al, %cl
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; SKX-NEXT: kmovw %k2, %eax
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; SKX-NEXT: andb $1, %al
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; SKX-NEXT: shlb $2, %al
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; SKX-NEXT: orb %cl, %al
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; SKX-NEXT: andb $1, %dil
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; SKX-NEXT: andb $1, %sil
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; SKX-NEXT: addb %sil, %sil
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; SKX-NEXT: orb %dil, %sil
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; SKX-NEXT: andb $1, %dl
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; SKX-NEXT: shlb $2, %dl
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; SKX-NEXT: orb %sil, %dl
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; SKX-NEXT: vpmovsxdq %xmm1, %ymm1
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; SKX-NEXT: vpsllq $2, %ymm1, %ymm1
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; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm0
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; SKX-NEXT: testb $1, %al
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; SKX-NEXT: testb $1, %dl
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; SKX-NEXT: jne .LBB31_1
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; SKX-NEXT: # %bb.2: # %else
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; SKX-NEXT: testb $2, %al
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; SKX-NEXT: testb $2, %dl
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; SKX-NEXT: jne .LBB31_3
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; SKX-NEXT: .LBB31_4: # %else2
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; SKX-NEXT: testb $4, %al
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; SKX-NEXT: testb $4, %dl
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; SKX-NEXT: jne .LBB31_5
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; SKX-NEXT: .LBB31_6: # %else5
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; SKX-NEXT: vmovdqa %xmm3, %xmm0
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; SKX-NEXT: vmovdqa %xmm2, %xmm0
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: retq
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; SKX-NEXT: .LBB31_1: # %cond.load
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; SKX-NEXT: vmovq %xmm0, %rcx
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; SKX-NEXT: vpinsrd $0, (%rcx), %xmm3, %xmm3
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; SKX-NEXT: testb $2, %al
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; SKX-NEXT: vmovq %xmm0, %rax
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; SKX-NEXT: vpinsrd $0, (%rax), %xmm2, %xmm2
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; SKX-NEXT: testb $2, %dl
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; SKX-NEXT: je .LBB31_4
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; SKX-NEXT: .LBB31_3: # %cond.load1
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; SKX-NEXT: vpextrq $1, %xmm0, %rcx
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; SKX-NEXT: vpinsrd $1, (%rcx), %xmm3, %xmm3
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; SKX-NEXT: testb $4, %al
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; SKX-NEXT: vpextrq $1, %xmm0, %rax
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; SKX-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2
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; SKX-NEXT: testb $4, %dl
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; SKX-NEXT: je .LBB31_6
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; SKX-NEXT: .LBB31_5: # %cond.load4
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; SKX-NEXT: vextracti128 $1, %ymm0, %xmm0
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; SKX-NEXT: vmovq %xmm0, %rax
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; SKX-NEXT: vpinsrd $2, (%rax), %xmm3, %xmm3
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; SKX-NEXT: vmovdqa %xmm3, %xmm0
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; SKX-NEXT: vpinsrd $2, (%rax), %xmm2, %xmm2
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; SKX-NEXT: vmovdqa %xmm2, %xmm0
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: retq
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;
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; SKX_32-LABEL: test30:
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; SKX_32: # %bb.0:
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; SKX_32-NEXT: subl $12, %esp
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; SKX_32-NEXT: .cfi_def_cfa_offset 16
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; SKX_32-NEXT: vmovdqa %xmm0, %xmm3
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; SKX_32-NEXT: vpslld $31, %xmm2, %xmm0
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; SKX_32-NEXT: vpmovd2m %xmm0, %k0
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; SKX_32-NEXT: kshiftrb $1, %k0, %k1
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; SKX_32-NEXT: kshiftrb $2, %k0, %k2
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; SKX_32-NEXT: kmovw %k0, %eax
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; SKX_32-NEXT: pushl %eax
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; SKX_32-NEXT: .cfi_def_cfa_offset 8
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; SKX_32-NEXT: movb {{[0-9]+}}(%esp), %al
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; SKX_32-NEXT: andb $1, %al
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; SKX_32-NEXT: kmovw %k1, %ecx
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; SKX_32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; SKX_32-NEXT: andb $1, %cl
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; SKX_32-NEXT: addb %cl, %cl
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; SKX_32-NEXT: orb %al, %cl
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; SKX_32-NEXT: kmovw %k2, %eax
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; SKX_32-NEXT: movb {{[0-9]+}}(%esp), %al
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; SKX_32-NEXT: andb $1, %al
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; SKX_32-NEXT: shlb $2, %al
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; SKX_32-NEXT: orb %cl, %al
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; SKX_32-NEXT: vmovdqa {{[0-9]+}}(%esp), %xmm0
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; SKX_32-NEXT: vpslld $2, %xmm1, %xmm1
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; SKX_32-NEXT: vpaddd %xmm1, %xmm3, %xmm1
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; SKX_32-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; SKX_32-NEXT: testb $1, %al
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; SKX_32-NEXT: jne .LBB31_1
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; SKX_32-NEXT: # %bb.2: # %else
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@ -1805,28 +1776,27 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x
|
||||
; SKX_32-NEXT: jne .LBB31_3
|
||||
; SKX_32-NEXT: .LBB31_4: # %else2
|
||||
; SKX_32-NEXT: testb $4, %al
|
||||
; SKX_32-NEXT: jne .LBB31_5
|
||||
; SKX_32-NEXT: je .LBB31_6
|
||||
; SKX_32-NEXT: .LBB31_5: # %cond.load4
|
||||
; SKX_32-NEXT: vpextrd $2, %xmm0, %eax
|
||||
; SKX_32-NEXT: vpinsrd $2, (%eax), %xmm2, %xmm2
|
||||
; SKX_32-NEXT: .LBB31_6: # %else5
|
||||
; SKX_32-NEXT: addl $12, %esp
|
||||
; SKX_32-NEXT: vmovdqa %xmm2, %xmm0
|
||||
; SKX_32-NEXT: popl %eax
|
||||
; SKX_32-NEXT: .cfi_def_cfa_offset 4
|
||||
; SKX_32-NEXT: retl
|
||||
; SKX_32-NEXT: .LBB31_1: # %cond.load
|
||||
; SKX_32-NEXT: .cfi_def_cfa_offset 16
|
||||
; SKX_32-NEXT: vmovd %xmm1, %ecx
|
||||
; SKX_32-NEXT: vpinsrd $0, (%ecx), %xmm0, %xmm0
|
||||
; SKX_32-NEXT: .cfi_def_cfa_offset 8
|
||||
; SKX_32-NEXT: vmovd %xmm0, %ecx
|
||||
; SKX_32-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2
|
||||
; SKX_32-NEXT: testb $2, %al
|
||||
; SKX_32-NEXT: je .LBB31_4
|
||||
; SKX_32-NEXT: .LBB31_3: # %cond.load1
|
||||
; SKX_32-NEXT: vpextrd $1, %xmm1, %ecx
|
||||
; SKX_32-NEXT: vpinsrd $1, (%ecx), %xmm0, %xmm0
|
||||
; SKX_32-NEXT: vpextrd $1, %xmm0, %ecx
|
||||
; SKX_32-NEXT: vpinsrd $1, (%ecx), %xmm2, %xmm2
|
||||
; SKX_32-NEXT: testb $4, %al
|
||||
; SKX_32-NEXT: je .LBB31_6
|
||||
; SKX_32-NEXT: .LBB31_5: # %cond.load4
|
||||
; SKX_32-NEXT: vpextrd $2, %xmm1, %eax
|
||||
; SKX_32-NEXT: vpinsrd $2, (%eax), %xmm0, %xmm0
|
||||
; SKX_32-NEXT: addl $12, %esp
|
||||
; SKX_32-NEXT: .cfi_def_cfa_offset 4
|
||||
; SKX_32-NEXT: retl
|
||||
; SKX_32-NEXT: jne .LBB31_5
|
||||
; SKX_32-NEXT: jmp .LBB31_6
|
||||
|
||||
%sext_ind = sext <3 x i32> %ind to <3 x i64>
|
||||
%gep.random = getelementptr i32, <3 x i32*> %base, <3 x i64> %sext_ind
|
||||
|
||||
@ -4913,12 +4913,24 @@ define void @widen_masked_store(<3 x i32> %v, <3 x i32>* %p, <3 x i1> %mask) {
|
||||
; AVX512F-LABEL: widen_masked_store:
|
||||
; AVX512F: ## %bb.0:
|
||||
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
|
||||
; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1
|
||||
; AVX512F-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
|
||||
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
|
||||
; AVX512F-NEXT: kmovw %edx, %k0
|
||||
; AVX512F-NEXT: andl $1, %esi
|
||||
; AVX512F-NEXT: kmovw %esi, %k1
|
||||
; AVX512F-NEXT: kxorw %k0, %k0, %k2
|
||||
; AVX512F-NEXT: kshiftrw $1, %k2, %k2
|
||||
; AVX512F-NEXT: kshiftlw $1, %k2, %k2
|
||||
; AVX512F-NEXT: korw %k1, %k2, %k1
|
||||
; AVX512F-NEXT: kshiftrw $1, %k1, %k2
|
||||
; AVX512F-NEXT: kxorw %k0, %k2, %k0
|
||||
; AVX512F-NEXT: kshiftlw $15, %k0, %k0
|
||||
; AVX512F-NEXT: kshiftrw $14, %k0, %k0
|
||||
; AVX512F-NEXT: kxorw %k0, %k1, %k0
|
||||
; AVX512F-NEXT: kshiftrw $2, %k0, %k1
|
||||
; AVX512F-NEXT: kmovw %ecx, %k2
|
||||
; AVX512F-NEXT: kxorw %k2, %k1, %k1
|
||||
; AVX512F-NEXT: kshiftlw $15, %k1, %k1
|
||||
; AVX512F-NEXT: kshiftrw $13, %k1, %k1
|
||||
; AVX512F-NEXT: kxorw %k1, %k0, %k0
|
||||
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
|
||||
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
|
||||
; AVX512F-NEXT: vmovdqu32 %zmm0, (%rdi) {%k1}
|
||||
@ -4927,24 +4939,48 @@ define void @widen_masked_store(<3 x i32> %v, <3 x i32>* %p, <3 x i1> %mask) {
|
||||
;
|
||||
; AVX512VLDQ-LABEL: widen_masked_store:
|
||||
; AVX512VLDQ: ## %bb.0:
|
||||
; AVX512VLDQ-NEXT: vpslld $31, %xmm1, %xmm1
|
||||
; AVX512VLDQ-NEXT: vpmovd2m %xmm1, %k0
|
||||
; AVX512VLDQ-NEXT: vpmovm2d %k0, %xmm1
|
||||
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLDQ-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
|
||||
; AVX512VLDQ-NEXT: vpmovd2m %xmm1, %k1
|
||||
; AVX512VLDQ-NEXT: kmovw %edx, %k0
|
||||
; AVX512VLDQ-NEXT: kmovw %esi, %k1
|
||||
; AVX512VLDQ-NEXT: kshiftlb $7, %k1, %k1
|
||||
; AVX512VLDQ-NEXT: kshiftrb $7, %k1, %k1
|
||||
; AVX512VLDQ-NEXT: kxorw %k0, %k0, %k2
|
||||
; AVX512VLDQ-NEXT: kshiftrb $1, %k2, %k2
|
||||
; AVX512VLDQ-NEXT: kshiftlb $1, %k2, %k2
|
||||
; AVX512VLDQ-NEXT: korb %k1, %k2, %k1
|
||||
; AVX512VLDQ-NEXT: kshiftrb $1, %k1, %k2
|
||||
; AVX512VLDQ-NEXT: kxorb %k0, %k2, %k0
|
||||
; AVX512VLDQ-NEXT: kshiftlb $7, %k0, %k0
|
||||
; AVX512VLDQ-NEXT: kshiftrb $6, %k0, %k0
|
||||
; AVX512VLDQ-NEXT: kxorb %k0, %k1, %k0
|
||||
; AVX512VLDQ-NEXT: kshiftrb $2, %k0, %k1
|
||||
; AVX512VLDQ-NEXT: kmovw %ecx, %k2
|
||||
; AVX512VLDQ-NEXT: kxorb %k2, %k1, %k1
|
||||
; AVX512VLDQ-NEXT: kshiftlb $7, %k1, %k1
|
||||
; AVX512VLDQ-NEXT: kshiftrb $5, %k1, %k1
|
||||
; AVX512VLDQ-NEXT: kxorw %k1, %k0, %k1
|
||||
; AVX512VLDQ-NEXT: vmovdqa32 %xmm0, (%rdi) {%k1}
|
||||
; AVX512VLDQ-NEXT: retq
|
||||
;
|
||||
; AVX512VLBW-LABEL: widen_masked_store:
|
||||
; AVX512VLBW: ## %bb.0:
|
||||
; AVX512VLBW-NEXT: vpslld $31, %xmm1, %xmm1
|
||||
; AVX512VLBW-NEXT: vptestmd %xmm1, %xmm1, %k1
|
||||
; AVX512VLBW-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; AVX512VLBW-NEXT: vmovdqa32 %xmm1, %xmm1 {%k1} {z}
|
||||
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLBW-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
|
||||
; AVX512VLBW-NEXT: vptestmd %xmm1, %xmm1, %k1
|
||||
; AVX512VLBW-NEXT: kmovd %edx, %k0
|
||||
; AVX512VLBW-NEXT: andl $1, %esi
|
||||
; AVX512VLBW-NEXT: kmovw %esi, %k1
|
||||
; AVX512VLBW-NEXT: kxorw %k0, %k0, %k2
|
||||
; AVX512VLBW-NEXT: kshiftrw $1, %k2, %k2
|
||||
; AVX512VLBW-NEXT: kshiftlw $1, %k2, %k2
|
||||
; AVX512VLBW-NEXT: korw %k1, %k2, %k1
|
||||
; AVX512VLBW-NEXT: kshiftrw $1, %k1, %k2
|
||||
; AVX512VLBW-NEXT: kxorw %k0, %k2, %k0
|
||||
; AVX512VLBW-NEXT: kshiftlw $15, %k0, %k0
|
||||
; AVX512VLBW-NEXT: kshiftrw $14, %k0, %k0
|
||||
; AVX512VLBW-NEXT: kxorw %k0, %k1, %k0
|
||||
; AVX512VLBW-NEXT: kshiftrw $2, %k0, %k1
|
||||
; AVX512VLBW-NEXT: kmovd %ecx, %k2
|
||||
; AVX512VLBW-NEXT: kxorw %k2, %k1, %k1
|
||||
; AVX512VLBW-NEXT: kshiftlw $15, %k1, %k1
|
||||
; AVX512VLBW-NEXT: kshiftrw $13, %k1, %k1
|
||||
; AVX512VLBW-NEXT: kxorw %k1, %k0, %k1
|
||||
; AVX512VLBW-NEXT: vmovdqa32 %xmm0, (%rdi) {%k1}
|
||||
; AVX512VLBW-NEXT: retq
|
||||
call void @llvm.masked.store.v3i32.p0v3i32(<3 x i32> %v, <3 x i32>* %p, i32 16, <3 x i1> %mask)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user