From a56b1c3d6855201c6c6a67aadbccca9084bf6d92 Mon Sep 17 00:00:00 2001 From: Elena Demikhovsky Date: Tue, 29 Mar 2016 06:55:56 +0000 Subject: [PATCH] Added 2 notes 1) Skylake and KNL support for X86 2) masked intrinsics load/store/gather/scatter Differential Revision: http://reviews.llvm.org/D18353 llvm-svn: 264703 --- docs/ReleaseNotes.rst | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index 982ade993b3..14fc126ce56 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -71,6 +71,13 @@ Non-comprehensive list of changes in this release Makes programs 10x faster by doing Special New Thing. +Changes to the LLVM IR +---------------------- + +* New intrinsics ``llvm.masked.load``, ``llvm.masked.store``, + ``llvm.masked.gather`` and ``llvm.masked.scatter`` were introduced to the + LLVM IR to allow selective memory access for vector data types. + Changes to the ARM Backend -------------------------- @@ -90,9 +97,15 @@ Changes to the PowerPC Target Changes to the X86 Target ------------------------------ +------------------------- - During this release ... +* LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512 + extensions using ``-march=skylake-avx512``. The switch enables the + ISA extensions AVX-512{F, CD, VL, BW, DQ}. + +* LLVM now supports the Intel CPU codenamed Knights Landing with AVX-512 + extensions using ``-march=knl``. The switch enables the ISA extensions + AVX-512{F, CD, ER, PF}. Changes to the AMDGPU Target -----------------------------