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[InstCombine] Split off SSE4a tests.
These aren't vector demanded bits tests. More tests to follow. llvm-svn: 243223
This commit is contained in:
Simon Pilgrim
parent
99e9fed5ff
commit
a58dfe82c9
@ -210,130 +210,6 @@ define <4 x float> @test_select(float %f, float %g) {
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ret <4 x float> %ret
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}
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; We should optimize these two redundant insertqi into one
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; CHECK: define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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; CHECK-NOT: insertqi
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 32)
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ret <2 x i64> %2
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}
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; The result of this insert is the second arg, since the top 64 bits of
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; the result are undefined, and we copy the bottom 64 bits from the
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; second arg
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; CHECK: define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> %i
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 0)
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ret <2 x i64> %1
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}
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; Test the several types of ranges and ordering that exist for two insertqi
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; CHECK: define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> %i
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 0)
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ret <2 x i64> %1
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}
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; CHECK: define <2 x i64> @testUndefinedInsertq_1(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testUndefinedInsertq_1(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> undef
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 16)
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ret <2 x i64> %1
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}
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; CHECK: define <2 x i64> @testUndefinedInsertq_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testUndefinedInsertq_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> undef
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 32)
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ret <2 x i64> %1
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}
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; CHECK: define <2 x i64> @testUndefinedInsertq_3(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testUndefinedInsertq_3(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> undef
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 16)
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ret <2 x i64> %1
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}
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; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertqi
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declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
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declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
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define <4 x float> @test_vpermilvar_ps(<4 x float> %v) {
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; CHECK-LABEL: @test_vpermilvar_ps(
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125
test/Transforms/InstCombine/x86-sse4a.ll
Normal file
125
test/Transforms/InstCombine/x86-sse4a.ll
Normal file
@ -0,0 +1,125 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; We should optimize these two redundant insertqi into one
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; CHECK: define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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; CHECK-NOT: insertqi
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 32)
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ret <2 x i64> %2
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}
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; The result of this insert is the second arg, since the top 64 bits of
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; the result are undefined, and we copy the bottom 64 bits from the
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; second arg
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; CHECK: define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> %i
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 0)
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ret <2 x i64> %1
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}
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; Test the several types of ranges and ordering that exist for two insertqi
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; CHECK: define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> %i
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 0)
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ret <2 x i64> %1
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}
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; CHECK: define <2 x i64> @testUndefinedInsertq_1(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testUndefinedInsertq_1(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> undef
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 16)
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
; CHECK: define <2 x i64> @testUndefinedInsertq_2(<2 x i64> %v, <2 x i64> %i)
|
||||
define <2 x i64> @testUndefinedInsertq_2(<2 x i64> %v, <2 x i64> %i) {
|
||||
; CHECK: ret <2 x i64> undef
|
||||
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 32)
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
; CHECK: define <2 x i64> @testUndefinedInsertq_3(<2 x i64> %v, <2 x i64> %i)
|
||||
define <2 x i64> @testUndefinedInsertq_3(<2 x i64> %v, <2 x i64> %i) {
|
||||
; CHECK: ret <2 x i64> undef
|
||||
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 16)
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertqi
|
||||
declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
|
||||
Loading…
Reference in New Issue
Block a user