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[mips][microMIPS] add lapc instruction

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Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D35984

llvm-svn: 312934
This commit is contained in:
Petar Jovanovic 2017-09-11 18:34:04 +00:00
parent 9745453d49
commit a5ac789396
17 changed files with 60 additions and 17 deletions
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3
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -1829,6 +1829,9 @@ def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //

3
lib/Target/Mips/Mips32r6InstrInfo.td
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@ -950,6 +950,9 @@ def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
GPR32Opnd:$rt)>, ISA_MIPS32R6; GPR32Opnd:$rt)>, ISA_MIPS32R6;
def : MipsInstAlias<"lapc $rd, $imm",
(ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Patterns and Pseudo Instructions // Patterns and Pseudo Instructions

2
test/MC/Disassembler/Mips/micromips32r6/valid.txt
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@ -32,7 +32,7 @@
0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234 0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234
0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5 0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0x78 0x80 0x00 0x19 # CHECK: lapc $4, 100
0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2

2
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
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@ -1,6 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56

2
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
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@ -193,7 +193,7 @@
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

2
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
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@ -1,6 +1,5 @@
# RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
@ -129,6 +128,7 @@
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256 0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
0x00 0x00 0x1b 0xd8 # CHECK: jrc $27 0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1) 0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456 0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18) 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)

2
test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
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@ -218,7 +218,7 @@
0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

4
test/MC/Mips/micromips32r6/invalid.s
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@ -38,6 +38,10 @@
# FIXME: This ought to point at the $34 but memory is treated as one operand. # FIXME: This ought to point at the $34 but memory is treated as one operand.
swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range

9
test/MC/Mips/micromips32r6/relocations.s
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@ -11,7 +11,10 @@
# CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: addiupc $2, bar # encoding: [0x78,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A]
@ -31,13 +34,15 @@
# CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x10 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
bc bar bc bar
addiupc $2,bar addiupc $2,bar
lapc $2,bar
lwpc $2,bar lwpc $2,bar
beqzc $3, bar beqzc $3, bar
bnezc $3, bar bnezc $3, bar

5
test/MC/Mips/micromips32r6/valid.s
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@ -4,7 +4,7 @@
add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10] add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2] addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83] addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
@ -63,6 +63,9 @@
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
lapc $7, 1048572 # CHECK: lapc $7, 1048572 # encoding: [0x78,0xe3,0xff,0xff]
lapc $7, -1048576 # CHECK: lapc $7, -1048576 # encoding: [0x78,0xe4,0x00,0x00]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08] lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]

11
test/MC/Mips/micromips64r6/relocations.s
View File

@ -11,7 +11,10 @@
# CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A] # CHECK-FIXUP: bc bar # encoding: [0b100101AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1 # CHECK-FIXUP: value: bar-4, kind: fixup_MICROMIPS_PC26_S1
# CHECK-FIXUP: addiupc $2, bar # encoding: [0x78,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lapc $2, bar # encoding: [0x78,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0x78,0b01001AAA,A,A]
@ -34,14 +37,16 @@
# CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0 # CHECK-ELF: 0x4 R_MICROMIPS_PC26_S1 bar 0x0
# CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x8 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0xC R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x10 R_MICROMIPS_PC18_S3 bar 0x0 # CHECK-ELF: 0x10 R_MICROMIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x14 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x14 R_MICROMIPS_PC18_S3 bar 0x0
# CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0 # CHECK-ELF: 0x18 R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: 0x1C R_MICROMIPS_PC21_S1 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
balc bar balc bar
bc bar bc bar
addiupc $2,bar addiupc $2,bar
lapc $2,bar
lwpc $2,bar lwpc $2,bar
ldpc $2, bar ldpc $2, bar
beqzc $3, bar beqzc $3, bar

4
test/MC/Mips/mips32r6/invalid.s
View File

@ -123,6 +123,10 @@ local_label:
evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4

7
test/MC/Mips/mips32r6/relocations.s
View File

@ -5,7 +5,7 @@
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
@ -34,6 +34,9 @@
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_lo(bar), # CHECK-FIXUP: value: %pcrel_lo(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 # CHECK-FIXUP: kind: fixup_MIPS_PCLO16
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A] # CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
@ -55,6 +58,7 @@
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 # CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
addiupc $2,bar addiupc $2,bar
@ -66,5 +70,6 @@
bc bar bc bar
aluipc $2, %pcrel_hi(bar) aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar) addiu $2, $2, %pcrel_lo(bar)
lapc $2,bar
lwpc $2,bar lwpc $2,bar
lwupc $2,bar lwupc $2,bar

3
test/MC/Mips/mips32r6/valid.s
View File

@ -16,7 +16,7 @@ a:
.set noat .set noat
# FIXME: Add the instructions carried forward from older ISA's # FIXME: Add the instructions carried forward from older ISA's
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
@ -113,6 +113,7 @@ a:
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08] l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08] l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]

4
test/MC/Mips/mips64r6/invalid.s
View File

@ -137,6 +137,10 @@ local_label:
evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction evp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
lapc $7, 1048576 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $6, -1048580 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lapc $3, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate

11
test/MC/Mips/mips64r6/relocations.s
View File

@ -5,7 +5,7 @@
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups. # Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] # CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
@ -34,6 +34,9 @@
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: %pcrel_lo(bar), # CHECK-FIXUP: value: %pcrel_lo(bar),
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 # CHECK-FIXUP: kind: fixup_MIPS_PCLO16
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
# CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A] # CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, # CHECK-FIXUP: value: bar,
@ -57,9 +60,10 @@
# CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC # CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
# CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x24 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x28 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: 0x30 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
# CHECK-ELF: ] # CHECK-ELF: ]
addiupc $2,bar addiupc $2,bar
@ -71,6 +75,7 @@
bc bar bc bar
aluipc $2, %pcrel_hi(bar) aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar) addiu $2, $2, %pcrel_lo(bar)
lapc $2,bar
ldpc $2,bar ldpc $2,bar
lwpc $2,bar lwpc $2,bar
lwupc $2,bar lwupc $2,bar

3
test/MC/Mips/mips64r6/valid.s
View File

@ -15,7 +15,7 @@
a: a:
.set noat .set noat
# FIXME: Add the instructions carried forward from older ISA's # FIXME: Add the instructions carried forward from older ISA's
addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
@ -158,6 +158,7 @@ a:
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08] l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08] l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48] ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48]
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]