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[AMDGPU] gfx1010 VOP1 instructions
Differential Revision: https://reviews.llvm.org/D61099 llvm-svn: 359225
This commit is contained in:
Stanislav Mekhanoshin
parent
a600614f1b
commit
a5aed97844
@ -1890,6 +1890,8 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableF32SrcMods = 0,
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getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret, "");
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field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
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field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
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field string TieRegDPP = "$old";
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}
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class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
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@ -2104,7 +2106,9 @@ def getMCOpcodeGen : InstrMapping {
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// does not actually change the encoding, and thus may be
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// removed later.
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[!cast<string>(SIEncodingFamily.GFX80)],
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[!cast<string>(SIEncodingFamily.GFX9)]];
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[!cast<string>(SIEncodingFamily.GFX9)],
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[!cast<string>(SIEncodingFamily.GFX10)],
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[!cast<string>(SIEncodingFamily.SDWA10)]];
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}
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// Get equivalent SOPK instruction.
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@ -169,13 +169,16 @@ def V_READFIRSTLANE_B32 :
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let Inst{31-25} = 0x3f; //encoding
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}
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let SchedRW = [WriteQuarterRate32] in {
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let SchedRW = [WriteDoubleCvt] in {
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defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64, fp_to_sint>;
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defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;
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defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;
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defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, fpextend>;
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defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>;
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defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
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} // End SchedRW = [WriteDoubleCvt]
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let SchedRW = [WriteQuarterRate32] in {
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defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;
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defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
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defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;
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@ -409,106 +412,221 @@ let SubtargetPredicate = isGFX9Only in {
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defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
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} // End SubtargetPredicate = isGFX9Only
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//===----------------------------------------------------------------------===//
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// Target
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isGFX10Plus in {
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defm V_PIPEFLUSH : VOP1Inst<"v_pipeflush", VOP_NONE>;
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let Uses = [M0] in {
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// FIXME-GFX10: Should V_MOVRELSD_2_B32 be VOP_NO_EXT?
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defm V_MOVRELSD_2_B32 :
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VOP1Inst<"v_movrelsd_2_b32", VOP_NO_EXT<VOP_I32_I32>>;
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def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
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let Constraints = "$vdst = $src1, $vdst1 = $src0";
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let DisableEncoding = "$vdst1,$src1";
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let SchedRW = [Write64Bit, Write64Bit];
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}
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} // End Uses = [M0]
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} // End SubtargetPredicate = isGFX10Plus
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//===----------------------------------------------------------------------===//
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// SI
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// Target-specific instruction encodings.
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//===----------------------------------------------------------------------===//
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multiclass VOP1_Real_si <bits<9> op> {
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let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "GFX6GFX7" in {
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def _e32_si :
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VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
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VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
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def _e64_si :
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VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
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VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
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}
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class VOP1_DPP<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
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VOP_DPP<ps.OpName, p> {
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let hasSideEffects = ps.hasSideEffects;
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let Defs = ps.Defs;
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let SchedRW = ps.SchedRW;
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let Uses = ps.Uses;
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bits<8> vdst;
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let Inst{8-0} = 0xfa;
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let Inst{16-9} = op;
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let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
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let Inst{31-25} = 0x3f;
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}
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defm V_NOP : VOP1_Real_si <0x0>;
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defm V_MOV_B32 : VOP1_Real_si <0x1>;
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defm V_CVT_I32_F64 : VOP1_Real_si <0x3>;
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defm V_CVT_F64_I32 : VOP1_Real_si <0x4>;
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defm V_CVT_F32_I32 : VOP1_Real_si <0x5>;
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defm V_CVT_F32_U32 : VOP1_Real_si <0x6>;
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defm V_CVT_U32_F32 : VOP1_Real_si <0x7>;
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defm V_CVT_I32_F32 : VOP1_Real_si <0x8>;
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defm V_MOV_FED_B32 : VOP1_Real_si <0x9>;
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defm V_CVT_F16_F32 : VOP1_Real_si <0xa>;
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defm V_CVT_F32_F16 : VOP1_Real_si <0xb>;
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defm V_CVT_RPI_I32_F32 : VOP1_Real_si <0xc>;
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defm V_CVT_FLR_I32_F32 : VOP1_Real_si <0xd>;
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defm V_CVT_OFF_F32_I4 : VOP1_Real_si <0xe>;
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defm V_CVT_F32_F64 : VOP1_Real_si <0xf>;
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defm V_CVT_F64_F32 : VOP1_Real_si <0x10>;
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defm V_CVT_F32_UBYTE0 : VOP1_Real_si <0x11>;
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defm V_CVT_F32_UBYTE1 : VOP1_Real_si <0x12>;
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defm V_CVT_F32_UBYTE2 : VOP1_Real_si <0x13>;
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defm V_CVT_F32_UBYTE3 : VOP1_Real_si <0x14>;
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defm V_CVT_U32_F64 : VOP1_Real_si <0x15>;
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defm V_CVT_F64_U32 : VOP1_Real_si <0x16>;
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defm V_FRACT_F32 : VOP1_Real_si <0x20>;
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defm V_TRUNC_F32 : VOP1_Real_si <0x21>;
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defm V_CEIL_F32 : VOP1_Real_si <0x22>;
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defm V_RNDNE_F32 : VOP1_Real_si <0x23>;
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defm V_FLOOR_F32 : VOP1_Real_si <0x24>;
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defm V_EXP_F32 : VOP1_Real_si <0x25>;
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defm V_LOG_CLAMP_F32 : VOP1_Real_si <0x26>;
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defm V_LOG_F32 : VOP1_Real_si <0x27>;
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defm V_RCP_CLAMP_F32 : VOP1_Real_si <0x28>;
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defm V_RCP_LEGACY_F32 : VOP1_Real_si <0x29>;
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defm V_RCP_F32 : VOP1_Real_si <0x2a>;
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defm V_RCP_IFLAG_F32 : VOP1_Real_si <0x2b>;
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defm V_RSQ_CLAMP_F32 : VOP1_Real_si <0x2c>;
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defm V_RSQ_LEGACY_F32 : VOP1_Real_si <0x2d>;
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defm V_RSQ_F32 : VOP1_Real_si <0x2e>;
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defm V_RCP_F64 : VOP1_Real_si <0x2f>;
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defm V_RCP_CLAMP_F64 : VOP1_Real_si <0x30>;
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defm V_RSQ_F64 : VOP1_Real_si <0x31>;
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defm V_RSQ_CLAMP_F64 : VOP1_Real_si <0x32>;
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defm V_SQRT_F32 : VOP1_Real_si <0x33>;
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defm V_SQRT_F64 : VOP1_Real_si <0x34>;
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defm V_SIN_F32 : VOP1_Real_si <0x35>;
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defm V_COS_F32 : VOP1_Real_si <0x36>;
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defm V_NOT_B32 : VOP1_Real_si <0x37>;
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defm V_BFREV_B32 : VOP1_Real_si <0x38>;
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defm V_FFBH_U32 : VOP1_Real_si <0x39>;
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defm V_FFBL_B32 : VOP1_Real_si <0x3a>;
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defm V_FFBH_I32 : VOP1_Real_si <0x3b>;
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defm V_FREXP_EXP_I32_F64 : VOP1_Real_si <0x3c>;
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defm V_FREXP_MANT_F64 : VOP1_Real_si <0x3d>;
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defm V_FRACT_F64 : VOP1_Real_si <0x3e>;
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defm V_FREXP_EXP_I32_F32 : VOP1_Real_si <0x3f>;
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defm V_FREXP_MANT_F32 : VOP1_Real_si <0x40>;
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defm V_CLREXCP : VOP1_Real_si <0x41>;
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defm V_MOVRELD_B32 : VOP1_Real_si <0x42>;
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defm V_MOVRELS_B32 : VOP1_Real_si <0x43>;
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defm V_MOVRELSD_B32 : VOP1_Real_si <0x44>;
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//===----------------------------------------------------------------------===//
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// CI
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// GFX10.
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//===----------------------------------------------------------------------===//
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multiclass VOP1_Real_ci <bits<9> op> {
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let AssemblerPredicates = [isGFX7Only], DecoderNamespace = "GFX7" in {
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def _e32_ci :
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let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
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multiclass VOP1Only_Real_gfx10<bits<9> op> {
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def _gfx10 :
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VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
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VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
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}
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multiclass VOP1_Real_e32_gfx10<bits<9> op> {
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def _e32_gfx10 :
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VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
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VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
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}
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multiclass VOP1_Real_e64_gfx10<bits<9> op> {
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def _e64_gfx10 :
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VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
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VOP3e_gfx10<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
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}
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multiclass VOP1_Real_sdwa_gfx10<bits<9> op> {
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def _sdwa_gfx10 :
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VOP_SDWA10_Real<!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
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VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
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let DecoderNamespace = "SDWA10";
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}
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}
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} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
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multiclass VOP1_Real_gfx10_no_dpp<bits<9> op> :
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VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
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VOP1_Real_sdwa_gfx10<op>;
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multiclass VOP1_Real_gfx10<bits<9> op> :
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VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
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VOP1_Real_sdwa_gfx10<op>;
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defm V_PIPEFLUSH : VOP1_Real_gfx10<0x01b>;
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defm V_MOVRELSD_2_B32 : VOP1_Real_gfx10<0x048>;
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defm V_CVT_F16_U16 : VOP1_Real_gfx10<0x050>;
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defm V_CVT_F16_I16 : VOP1_Real_gfx10<0x051>;
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defm V_CVT_U16_F16 : VOP1_Real_gfx10<0x052>;
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defm V_CVT_I16_F16 : VOP1_Real_gfx10<0x053>;
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defm V_RCP_F16 : VOP1_Real_gfx10<0x054>;
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defm V_SQRT_F16 : VOP1_Real_gfx10<0x055>;
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defm V_RSQ_F16 : VOP1_Real_gfx10<0x056>;
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defm V_LOG_F16 : VOP1_Real_gfx10<0x057>;
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defm V_EXP_F16 : VOP1_Real_gfx10<0x058>;
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defm V_FREXP_MANT_F16 : VOP1_Real_gfx10<0x059>;
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defm V_FREXP_EXP_I16_F16 : VOP1_Real_gfx10<0x05a>;
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defm V_FLOOR_F16 : VOP1_Real_gfx10<0x05b>;
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defm V_CEIL_F16 : VOP1_Real_gfx10<0x05c>;
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defm V_TRUNC_F16 : VOP1_Real_gfx10<0x05d>;
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defm V_RNDNE_F16 : VOP1_Real_gfx10<0x05e>;
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defm V_FRACT_F16 : VOP1_Real_gfx10<0x05f>;
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defm V_SIN_F16 : VOP1_Real_gfx10<0x060>;
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defm V_COS_F16 : VOP1_Real_gfx10<0x061>;
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defm V_SAT_PK_U8_I16 : VOP1_Real_gfx10<0x062>;
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defm V_CVT_NORM_I16_F16 : VOP1_Real_gfx10<0x063>;
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defm V_CVT_NORM_U16_F16 : VOP1_Real_gfx10<0x064>;
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defm V_SWAP_B32 : VOP1Only_Real_gfx10<0x065>;
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defm V_SWAPREL_B32 : VOP1Only_Real_gfx10<0x068>;
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//===----------------------------------------------------------------------===//
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// GFX7, GFX10.
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//===----------------------------------------------------------------------===//
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let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
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multiclass VOP1_Real_e32_gfx7<bits<9> op> {
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def _e32_gfx7 :
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VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
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VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
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def _e64_ci :
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VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
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VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
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}
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}
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multiclass VOP1_Real_e64_gfx7<bits<9> op> {
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def _e64_gfx7 :
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VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
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VOP3e_gfx6_gfx7<{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
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}
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} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
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defm V_TRUNC_F64 : VOP1_Real_ci <0x17>;
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defm V_CEIL_F64 : VOP1_Real_ci <0x18>;
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defm V_FLOOR_F64 : VOP1_Real_ci <0x1A>;
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defm V_RNDNE_F64 : VOP1_Real_ci <0x19>;
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defm V_LOG_LEGACY_F32 : VOP1_Real_ci <0x45>;
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defm V_EXP_LEGACY_F32 : VOP1_Real_ci <0x46>;
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multiclass VOP1_Real_gfx7<bits<9> op> :
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VOP1_Real_e32_gfx7<op>, VOP1_Real_e64_gfx7<op>;
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multiclass VOP1_Real_gfx7_gfx10<bits<9> op> :
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VOP1_Real_gfx7<op>, VOP1_Real_gfx10<op>;
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defm V_LOG_LEGACY_F32 : VOP1_Real_gfx7<0x045>;
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defm V_EXP_LEGACY_F32 : VOP1_Real_gfx7<0x046>;
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defm V_TRUNC_F64 : VOP1_Real_gfx7_gfx10<0x017>;
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defm V_CEIL_F64 : VOP1_Real_gfx7_gfx10<0x018>;
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defm V_RNDNE_F64 : VOP1_Real_gfx7_gfx10<0x019>;
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defm V_FLOOR_F64 : VOP1_Real_gfx7_gfx10<0x01a>;
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//===----------------------------------------------------------------------===//
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// GFX6, GFX7, GFX10.
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//===----------------------------------------------------------------------===//
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let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
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multiclass VOP1_Real_e32_gfx6_gfx7<bits<9> op> {
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def _e32_gfx6_gfx7 :
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VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
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VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
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}
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multiclass VOP1_Real_e64_gfx6_gfx7<bits<9> op> {
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def _e64_gfx6_gfx7 :
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VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
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VOP3e_gfx6_gfx7<{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
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}
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} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
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multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :
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VOP1_Real_e32_gfx6_gfx7<op>, VOP1_Real_e64_gfx6_gfx7<op>;
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multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :
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VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;
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multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp<bits<9> op> :
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VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp<op>;
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defm V_LOG_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x026>;
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defm V_RCP_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x028>;
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defm V_RCP_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x029>;
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defm V_RSQ_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x02c>;
|
||||
defm V_RSQ_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x02d>;
|
||||
defm V_RCP_CLAMP_F64 : VOP1_Real_gfx6_gfx7<0x030>;
|
||||
defm V_RSQ_CLAMP_F64 : VOP1_Real_gfx6_gfx7<0x032>;
|
||||
|
||||
defm V_NOP : VOP1_Real_gfx6_gfx7_gfx10<0x000>;
|
||||
defm V_MOV_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x001>;
|
||||
defm V_CVT_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x003>;
|
||||
defm V_CVT_F64_I32 : VOP1_Real_gfx6_gfx7_gfx10<0x004>;
|
||||
defm V_CVT_F32_I32 : VOP1_Real_gfx6_gfx7_gfx10<0x005>;
|
||||
defm V_CVT_F32_U32 : VOP1_Real_gfx6_gfx7_gfx10<0x006>;
|
||||
defm V_CVT_U32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x007>;
|
||||
defm V_CVT_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x008>;
|
||||
defm V_MOV_FED_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x009>;
|
||||
defm V_CVT_F16_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00a>;
|
||||
defm V_CVT_F32_F16 : VOP1_Real_gfx6_gfx7_gfx10<0x00b>;
|
||||
defm V_CVT_RPI_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00c>;
|
||||
defm V_CVT_FLR_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00d>;
|
||||
defm V_CVT_OFF_F32_I4 : VOP1_Real_gfx6_gfx7_gfx10<0x00e>;
|
||||
defm V_CVT_F32_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x00f>;
|
||||
defm V_CVT_F64_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x010>;
|
||||
defm V_CVT_F32_UBYTE0 : VOP1_Real_gfx6_gfx7_gfx10<0x011>;
|
||||
defm V_CVT_F32_UBYTE1 : VOP1_Real_gfx6_gfx7_gfx10<0x012>;
|
||||
defm V_CVT_F32_UBYTE2 : VOP1_Real_gfx6_gfx7_gfx10<0x013>;
|
||||
defm V_CVT_F32_UBYTE3 : VOP1_Real_gfx6_gfx7_gfx10<0x014>;
|
||||
defm V_CVT_U32_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x015>;
|
||||
defm V_CVT_F64_U32 : VOP1_Real_gfx6_gfx7_gfx10<0x016>;
|
||||
defm V_FRACT_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x020>;
|
||||
defm V_TRUNC_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x021>;
|
||||
defm V_CEIL_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x022>;
|
||||
defm V_RNDNE_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x023>;
|
||||
defm V_FLOOR_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x024>;
|
||||
defm V_EXP_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x025>;
|
||||
defm V_LOG_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x027>;
|
||||
defm V_RCP_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x02a>;
|
||||
defm V_RCP_IFLAG_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x02b>;
|
||||
defm V_RSQ_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x02e>;
|
||||
defm V_RCP_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x02f>;
|
||||
defm V_RSQ_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x031>;
|
||||
defm V_SQRT_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x033>;
|
||||
defm V_SQRT_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x034>;
|
||||
defm V_SIN_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x035>;
|
||||
defm V_COS_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x036>;
|
||||
defm V_NOT_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x037>;
|
||||
defm V_BFREV_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x038>;
|
||||
defm V_FFBH_U32 : VOP1_Real_gfx6_gfx7_gfx10<0x039>;
|
||||
defm V_FFBL_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x03a>;
|
||||
defm V_FFBH_I32 : VOP1_Real_gfx6_gfx7_gfx10<0x03b>;
|
||||
defm V_FREXP_EXP_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x03c>;
|
||||
defm V_FREXP_MANT_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x03d>;
|
||||
defm V_FRACT_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x03e>;
|
||||
defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x03f>;
|
||||
defm V_FREXP_MANT_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x040>;
|
||||
defm V_CLREXCP : VOP1_Real_gfx6_gfx7_gfx10<0x041>;
|
||||
defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x042>;
|
||||
defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x043>;
|
||||
defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x044>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX8, GFX9 (VI).
|
||||
|
||||
@ -731,13 +731,13 @@ multiclass VOP2_Real_e32_si <bits<6> op> {
|
||||
multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
|
||||
def _e64_si :
|
||||
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
||||
VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
||||
VOP3e_gfx6_gfx7 <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
||||
}
|
||||
|
||||
multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
|
||||
def _e64_si :
|
||||
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
||||
VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
||||
VOP3be_gfx6_gfx7 <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
|
||||
}
|
||||
|
||||
} // End AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "GFX6GFX7"
|
||||
|
||||
@ -671,12 +671,12 @@ let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "GFX6GFX7" in {
|
||||
|
||||
multiclass VOP3_Real_si<bits<9> op> {
|
||||
def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
|
||||
VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
VOP3e_gfx6_gfx7 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
}
|
||||
|
||||
multiclass VOP3be_Real_si<bits<9> op> {
|
||||
def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
|
||||
VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
VOP3be_gfx6_gfx7 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
}
|
||||
|
||||
} // End AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "GFX6GFX7"
|
||||
@ -740,7 +740,7 @@ defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
|
||||
|
||||
multiclass VOP3_Real_ci<bits<9> op> {
|
||||
def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
|
||||
VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
|
||||
VOP3e_gfx6_gfx7 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
|
||||
let AssemblerPredicates = [isGFX7Only];
|
||||
let DecoderNamespace = "GFX7";
|
||||
}
|
||||
@ -748,7 +748,7 @@ multiclass VOP3_Real_ci<bits<9> op> {
|
||||
|
||||
multiclass VOP3be_Real_ci<bits<9> op> {
|
||||
def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
|
||||
VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
|
||||
VOP3be_gfx6_gfx7 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
|
||||
let AssemblerPredicates = [isGFX7Only];
|
||||
let DecoderNamespace = "GFX7";
|
||||
}
|
||||
|
||||
@ -708,8 +708,8 @@ multiclass VOPC_Real_si <bits<9> op> {
|
||||
VOPCe<op{7-0}>;
|
||||
|
||||
def _e64_si :
|
||||
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
||||
VOP3a_si <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
|
||||
VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
|
||||
VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
|
||||
// Encoding used for VOPC instructions encoded as VOP3
|
||||
// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
|
||||
bits<8> sdst;
|
||||
|
||||
@ -188,9 +188,15 @@ class VOP3a<VOPProfile P> : Enc64 {
|
||||
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
|
||||
}
|
||||
|
||||
class VOP3a_si <bits<9> op, VOPProfile P> : VOP3a<P> {
|
||||
class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> {
|
||||
let Inst{11} = !if(p.HasClamp, clamp{0}, 0);
|
||||
let Inst{25-17} = op;
|
||||
let Inst{11} = !if(P.HasClamp, clamp{0}, 0);
|
||||
}
|
||||
|
||||
class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> {
|
||||
let Inst{15} = !if(p.HasClamp, clamp{0}, 0);
|
||||
let Inst{25-16} = op;
|
||||
let Inst{31-26} = 0x35;
|
||||
}
|
||||
|
||||
class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
|
||||
@ -198,9 +204,14 @@ class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
|
||||
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
|
||||
}
|
||||
|
||||
class VOP3e_si <bits<9> op, VOPProfile P> : VOP3a_si <op, P> {
|
||||
class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> {
|
||||
bits<8> vdst;
|
||||
let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
|
||||
let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
|
||||
}
|
||||
|
||||
class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> {
|
||||
bits<8> vdst;
|
||||
let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
|
||||
}
|
||||
|
||||
class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
|
||||
@ -215,6 +226,13 @@ class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
|
||||
let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
|
||||
}
|
||||
|
||||
class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
|
||||
let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
|
||||
let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0);
|
||||
let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0);
|
||||
let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0);
|
||||
}
|
||||
|
||||
// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
|
||||
class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
|
||||
bits<2> attrchan;
|
||||
@ -234,6 +252,21 @@ class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
|
||||
let Inst{49-41} = src0;
|
||||
}
|
||||
|
||||
class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
|
||||
bits<6> attr;
|
||||
bits<2> attrchan;
|
||||
bits<1> high;
|
||||
|
||||
let Inst{8} = 0;
|
||||
let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0);
|
||||
let Inst{37-32} = attr;
|
||||
let Inst{39-38} = attrchan;
|
||||
let Inst{40} = !if(p.HasHigh, high, 0);
|
||||
let Inst{49-41} = src0;
|
||||
let Inst{61} = 0;
|
||||
let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0);
|
||||
}
|
||||
|
||||
class VOP3be <VOPProfile P> : Enc64 {
|
||||
bits<8> vdst;
|
||||
bits<2> src0_modifiers;
|
||||
@ -293,10 +326,21 @@ class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
|
||||
let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo)
|
||||
}
|
||||
|
||||
class VOP3be_si <bits<9> op, VOPProfile P> : VOP3be<P> {
|
||||
class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> {
|
||||
let Inst{31-26} = 0x33; //encoding
|
||||
}
|
||||
|
||||
class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {
|
||||
let Inst{25-17} = op;
|
||||
}
|
||||
|
||||
class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> {
|
||||
bits<1> clamp;
|
||||
let Inst{15} = !if(p.HasClamp, clamp{0}, 0);
|
||||
let Inst{25-16} = op;
|
||||
let Inst{31-26} = 0x35;
|
||||
}
|
||||
|
||||
class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
|
||||
bits<1> clamp;
|
||||
let Inst{25-16} = op;
|
||||
@ -391,7 +435,7 @@ class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> {
|
||||
class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> {
|
||||
bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
|
||||
|
||||
let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, 0);
|
||||
let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
|
||||
let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
|
||||
}
|
||||
|
||||
@ -454,9 +498,8 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
|
||||
let TSFlags = ps.TSFlags;
|
||||
}
|
||||
|
||||
class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
|
||||
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []>,
|
||||
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9> {
|
||||
class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
|
||||
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> {
|
||||
|
||||
let isPseudo = 0;
|
||||
let isCodeGenOnly = 0;
|
||||
@ -483,6 +526,19 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
|
||||
let TSFlags = ps.TSFlags;
|
||||
}
|
||||
|
||||
class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
|
||||
Base_VOP_SDWA9_Real <ps >,
|
||||
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
|
||||
|
||||
class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
|
||||
let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
|
||||
let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
|
||||
let DecoderNamespace = "SDWA10";
|
||||
}
|
||||
|
||||
class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> :
|
||||
Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>;
|
||||
|
||||
class VOP_DPPe<VOPProfile P> : Enc64 {
|
||||
bits<2> src0_modifiers;
|
||||
bits<8> src0;
|
||||
@ -491,6 +547,7 @@ class VOP_DPPe<VOPProfile P> : Enc64 {
|
||||
bits<1> bound_ctrl;
|
||||
bits<4> bank_mask;
|
||||
bits<4> row_mask;
|
||||
bit fi;
|
||||
|
||||
let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
|
||||
let Inst{48-40} = dpp_ctrl;
|
||||
@ -531,8 +588,8 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
|
||||
let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
|
||||
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
|
||||
AMDGPUAsmVariants.Disable);
|
||||
let Constraints = !if(P.NumSrcArgs, "$old = $vdst", "");
|
||||
let DisableEncoding = !if(P.NumSrcArgs, "$old", "");
|
||||
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
|
||||
let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
|
||||
let DecoderNamespace = "DPP";
|
||||
|
||||
VOPProfile Pfl = P;
|
||||
@ -566,6 +623,31 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
|
||||
let TSFlags = ps.TSFlags;
|
||||
}
|
||||
|
||||
class VOP_DPP <string OpName, VOPProfile P,
|
||||
dag InsDPP = P.InsDPP,
|
||||
string AsmDPP = P.AsmDPP> :
|
||||
InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>,
|
||||
VOP_DPPe<P> {
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
let UseNamedOperandTable = 1;
|
||||
|
||||
let VALU = 1;
|
||||
let DPP = 1;
|
||||
let Size = 8;
|
||||
|
||||
let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
|
||||
let SubtargetPredicate = HasDPP;
|
||||
let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
|
||||
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
|
||||
AMDGPUAsmVariants.Disable);
|
||||
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
|
||||
let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
|
||||
let DecoderNamespace = "DPP";
|
||||
}
|
||||
|
||||
class getNumNodeArgs<SDPatternOperator Op> {
|
||||
SDNode N = !cast<SDNode>(Op);
|
||||
SDTypeProfile TP = N.TypeProfile;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user