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simplify this code a bit now that "allocation to a vreg class" can never
fail. llvm-svn: 67616
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@ -4929,9 +4929,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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// Otherwise, if this was a reference to an LLVM register class, create vregs
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// for this reference.
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std::vector<unsigned> RegClassRegs;
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const TargetRegisterClass *RC = PhysReg.second;
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if (RC) {
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if (PhysReg.second != 0) {
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RegVT = *PhysReg.second->vt_begin();
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if (OpInfo.ConstraintVT == MVT::Other)
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ValueVT = RegVT;
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@ -4943,13 +4941,14 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
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return;
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} else {
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// This is a reference to a register class that doesn't directly correspond
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// to an LLVM register class. Allocate NumRegs consecutive, available,
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// registers from the class.
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RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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}
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// This is a reference to a register class that doesn't directly correspond
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// to an LLVM register class. Allocate NumRegs consecutive, available,
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// registers from the class.
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std::vector<unsigned> RegClassRegs
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= TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
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unsigned NumAllocated = 0;
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@ -4965,13 +4964,11 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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// Check to see if this register is allocatable (i.e. don't give out the
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// stack pointer).
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if (RC == 0) {
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RC = isAllocatableRegister(Reg, MF, TLI, TRI);
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if (!RC) { // Couldn't allocate this register.
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// Reset NumAllocated to make sure we return consecutive registers.
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NumAllocated = 0;
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continue;
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}
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const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
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if (!RC) { // Couldn't allocate this register.
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// Reset NumAllocated to make sure we return consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Okay, this register is good, we can use it.
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