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[X86] Add a test case showing failure to use the RMW form of ADC when the load is in operand 1 going into isel.

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The ADC instruction is commutable, but we only have RMW isel patterns with a load on the left hand side. Nothing will canonicalize loads to the LHS on these ops. So we need two patterns.

llvm-svn: 341605
This commit is contained in:
Craig Topper 2018-09-06 23:55:34 +00:00
parent 77eea16d51
commit a62685a203
1 changed files with 28 additions and 0 deletions
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28
test/CodeGen/X86/addcarry.ll
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@ -14,6 +14,34 @@ entry:
ret i128 %0
}
define void @add128_rmw(i128* %a, i128 %b) nounwind {
; CHECK-LABEL: add128_rmw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addq %rsi, (%rdi)
; CHECK-NEXT: adcq %rdx, 8(%rdi)
; CHECK-NEXT: retq
entry:
%0 = load i128, i128* %a
%1 = add i128 %0, %b
store i128 %1, i128* %a
ret void
}
define void @add128_rmw2(i128 %a, i128* %b) nounwind {
; CHECK-LABEL: add128_rmw2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addq (%rdx), %rdi
; CHECK-NEXT: adcq 8(%rdx), %rsi
; CHECK-NEXT: movq %rdi, (%rdx)
; CHECK-NEXT: movq %rsi, 8(%rdx)
; CHECK-NEXT: retq
entry:
%0 = load i128, i128* %b
%1 = add i128 %a, %0
store i128 %1, i128* %b
ret void
}
define i256 @add256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: add256:
; CHECK: # %bb.0: # %entry