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TableGen: Check the dynamic type of !cast<Rec>(string)
Summary: The docs already claim that this happens, but so far it hasn't. As a consequence, existing TableGen files get this wrong a lot, but luckily the fixes are all reasonably straightforward. To make this work with all the existing forms of self-references (since the true type of a record is only built up over time), the lookup of self-references in !cast is delayed until the final resolving step. Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D44475 llvm-svn: 327849
This commit is contained in:
Nicolai Haehnle
parent
74a4d54f41
commit
a64a4772e8
@ -788,7 +788,7 @@ public:
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// Fold - If possible, fold this to a simpler init. Return this if not
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// possible to fold.
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Init *Fold(Record *CurRec) const;
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Init *Fold(Record *CurRec, bool IsFinal = false) const;
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Init *resolveReferences(Resolver &R) const override;
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@ -1497,6 +1497,9 @@ public:
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/// If there are any field references that refer to fields
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/// that have been filled in, we can propagate the values now.
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///
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/// This is a final resolve: any error messages, e.g. due to undefined
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/// !cast references, are generated now.
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void resolveReferences();
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/// Apply the resolver to the name of the record as well as to the
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@ -1786,6 +1789,7 @@ Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,
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/// Init::resolveReferences.
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class Resolver {
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Record *CurRec;
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bool IsFinal = false;
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public:
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explicit Resolver(Record *CurRec) : CurRec(CurRec) {}
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@ -1801,6 +1805,13 @@ public:
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// result in a ? (UnsetInit). This behavior is used to represent instruction
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// encodings by keeping references to unset variables within a record.
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virtual bool keepUnsetBits() const { return false; }
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// Whether this is the final resolve step before adding a record to the
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// RecordKeeper. Error reporting during resolve and related constant folding
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// should only happen when this is true.
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bool isFinal() const { return IsFinal; }
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void setFinal(bool Final) { IsFinal = Final; }
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};
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/// Resolve arbitrary mappings.
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@ -1861,7 +1872,10 @@ class ShadowResolver final : public Resolver {
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DenseSet<Init *> Shadowed;
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public:
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explicit ShadowResolver(Resolver &R) : Resolver(R.getCurrentRecord()), R(R) {}
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explicit ShadowResolver(Resolver &R)
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: Resolver(R.getCurrentRecord()), R(R) {
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setFinal(R.isFinal());
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}
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void addShadow(Init *Key) { Shadowed.insert(Key); }
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@ -1132,27 +1132,27 @@ def setne : PatFrag<(ops node:$lhs, node:$rhs),
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multiclass binary_atomic_op_ord<SDNode atomic_op> {
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def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingMonotonic = 1;
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}
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def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquire = 1;
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}
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def #NAME#_release : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingRelease = 1;
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}
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def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquireRelease = 1;
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}
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def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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@ -1160,27 +1160,27 @@ multiclass binary_atomic_op_ord<SDNode atomic_op> {
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multiclass ternary_atomic_op_ord<SDNode atomic_op> {
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def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingMonotonic = 1;
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}
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def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquire = 1;
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}
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def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingRelease = 1;
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}
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def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquireRelease = 1;
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}
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def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDNode>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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@ -194,7 +194,7 @@ void RecordRecTy::Profile(FoldingSetNodeID &ID) const {
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std::string RecordRecTy::getAsString() const {
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if (NumClasses == 1)
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return getClasses()[0]->getName();
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return getClasses()[0]->getNameInitAsString();
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std::string Str = "{";
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bool First = true;
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@ -202,7 +202,7 @@ std::string RecordRecTy::getAsString() const {
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if (!First)
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Str += ", ";
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First = false;
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Str += R->getName();
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Str += R->getNameInitAsString();
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}
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Str += "}";
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return Str;
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@ -700,7 +700,7 @@ void UnOpInit::Profile(FoldingSetNodeID &ID) const {
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ProfileUnOpInit(ID, getOpcode(), getOperand(), getType());
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}
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Init *UnOpInit::Fold(Record *CurRec) const {
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Init *UnOpInit::Fold(Record *CurRec, bool IsFinal) const {
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switch (getOpcode()) {
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case CAST:
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if (isa<StringRecTy>(getType())) {
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@ -715,12 +715,34 @@ Init *UnOpInit::Fold(Record *CurRec) const {
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} else if (isa<RecordRecTy>(getType())) {
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if (StringInit *Name = dyn_cast<StringInit>(LHS)) {
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assert(CurRec && "NULL pointer");
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if (Record *D = (CurRec->getRecords()).getDef(Name->getValue()))
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return DefInit::get(D);
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Record *D;
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PrintFatalError(CurRec->getLoc(),
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Twine("Undefined reference to record: '") +
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Name->getValue() + "'\n");
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// Self-references are allowed, but their resolution is delayed until
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// the final resolve to ensure that we get the correct type for them.
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if (Name == CurRec->getNameInit()) {
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if (!IsFinal)
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break;
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D = CurRec;
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} else {
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D = CurRec->getRecords().getDef(Name->getValue());
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if (!D) {
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if (IsFinal)
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PrintFatalError(CurRec->getLoc(),
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Twine("Undefined reference to record: '") +
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Name->getValue() + "'\n");
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break;
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}
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}
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DefInit *DI = DefInit::get(D);
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if (!DI->getType()->typeIsA(getType())) {
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PrintFatalError(CurRec->getLoc(),
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Twine("Expected type '") +
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getType()->getAsString() + "', got '" +
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DI->getType()->getAsString() + "' in: " +
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getAsString() + "\n");
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}
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return DI;
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}
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}
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@ -762,9 +784,9 @@ Init *UnOpInit::Fold(Record *CurRec) const {
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Init *UnOpInit::resolveReferences(Resolver &R) const {
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Init *lhs = LHS->resolveReferences(R);
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if (LHS != lhs)
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if (LHS != lhs || (R.isFinal() && getOpcode() == CAST))
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return (UnOpInit::get(getOpcode(), lhs, getType()))
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->Fold(R.getCurrentRecord());
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->Fold(R.getCurrentRecord(), R.isFinal());
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return const_cast<UnOpInit *>(this);
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}
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@ -1904,6 +1926,7 @@ void Record::resolveReferences(Resolver &R, const RecordVal *SkipVal) {
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void Record::resolveReferences() {
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RecordResolver R(*this);
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R.setFinal(true);
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resolveReferences(R);
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}
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@ -5931,10 +5931,10 @@ multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
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multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
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SDPatternOperator OpNode = null_frag> {
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def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
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(ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
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(ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
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asm, []>;
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def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
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(ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
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(ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
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asm, []>;
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}
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@ -8789,7 +8789,7 @@ class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
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class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
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Operand listtype>
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DAGOperand listtype>
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: BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
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(outs listtype:$Vt), (ins GPR64sp:$Rn),
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[]> {
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@ -8801,7 +8801,7 @@ class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
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}
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let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
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class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
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string asm, Operand listtype, Operand GPR64pi>
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string asm, DAGOperand listtype, DAGOperand GPR64pi>
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: BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
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"$Rn = $wback",
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(outs GPR64sp:$wback, listtype:$Vt),
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@ -8859,46 +8859,46 @@ multiclass SIMDLdrAliases<string asm, string layout, string Count,
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multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
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int Offset1, int Offset2, int Offset4, int Offset8> {
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def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
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!cast<Operand>("VecList" # Count # "8b")>;
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!cast<DAGOperand>("VecList" # Count # "8b")>;
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def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
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!cast<Operand>("VecList" # Count #"16b")>;
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!cast<DAGOperand>("VecList" # Count #"16b")>;
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def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
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!cast<Operand>("VecList" # Count #"4h")>;
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!cast<DAGOperand>("VecList" # Count #"4h")>;
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def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
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!cast<Operand>("VecList" # Count #"8h")>;
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!cast<DAGOperand>("VecList" # Count #"8h")>;
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def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
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!cast<Operand>("VecList" # Count #"2s")>;
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!cast<DAGOperand>("VecList" # Count #"2s")>;
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def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
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!cast<Operand>("VecList" # Count #"4s")>;
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!cast<DAGOperand>("VecList" # Count #"4s")>;
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def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
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!cast<Operand>("VecList" # Count #"1d")>;
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!cast<DAGOperand>("VecList" # Count #"1d")>;
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def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
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!cast<Operand>("VecList" # Count #"2d")>;
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!cast<DAGOperand>("VecList" # Count #"2d")>;
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def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
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!cast<Operand>("VecList" # Count # "8b"),
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!cast<Operand>("GPR64pi" # Offset1)>;
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!cast<DAGOperand>("VecList" # Count # "8b"),
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!cast<DAGOperand>("GPR64pi" # Offset1)>;
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def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
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!cast<Operand>("VecList" # Count # "16b"),
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!cast<Operand>("GPR64pi" # Offset1)>;
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!cast<DAGOperand>("VecList" # Count # "16b"),
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!cast<DAGOperand>("GPR64pi" # Offset1)>;
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def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
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!cast<Operand>("VecList" # Count # "4h"),
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!cast<Operand>("GPR64pi" # Offset2)>;
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!cast<DAGOperand>("VecList" # Count # "4h"),
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!cast<DAGOperand>("GPR64pi" # Offset2)>;
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def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
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!cast<Operand>("VecList" # Count # "8h"),
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!cast<Operand>("GPR64pi" # Offset2)>;
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!cast<DAGOperand>("VecList" # Count # "8h"),
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!cast<DAGOperand>("GPR64pi" # Offset2)>;
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def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
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!cast<Operand>("VecList" # Count # "2s"),
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!cast<Operand>("GPR64pi" # Offset4)>;
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!cast<DAGOperand>("VecList" # Count # "2s"),
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!cast<DAGOperand>("GPR64pi" # Offset4)>;
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def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
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!cast<Operand>("VecList" # Count # "4s"),
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!cast<Operand>("GPR64pi" # Offset4)>;
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!cast<DAGOperand>("VecList" # Count # "4s"),
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!cast<DAGOperand>("GPR64pi" # Offset4)>;
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def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
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!cast<Operand>("VecList" # Count # "1d"),
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!cast<Operand>("GPR64pi" # Offset8)>;
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!cast<DAGOperand>("VecList" # Count # "1d"),
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!cast<DAGOperand>("GPR64pi" # Offset8)>;
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def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
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!cast<Operand>("VecList" # Count # "2d"),
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!cast<Operand>("GPR64pi" # Offset8)>;
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!cast<DAGOperand>("VecList" # Count # "2d"),
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!cast<DAGOperand>("GPR64pi" # Offset8)>;
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defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
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defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
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@ -9300,9 +9300,9 @@ multiclass SIMDLdSt4SingleAliases<string asm> {
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let Predicates = [HasNEON, HasRDM] in {
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class BaseSIMDThreeSameVectorTiedR0<bit Q, bit U, bits<2> size, bits<5> opcode,
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RegisterOperand regtype, string asm,
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RegisterOperand regtype, string asm,
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string kind, list<dag> pattern>
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: BaseSIMDThreeSameVectorTied<Q, U, {size,0}, opcode, regtype, asm, kind,
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: BaseSIMDThreeSameVectorTied<Q, U, {size,0}, opcode, regtype, asm, kind,
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pattern> {
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}
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multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
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@ -9311,7 +9311,7 @@ multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
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[(set (v4i16 V64:$dst),
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(Accum (v4i16 V64:$Rd),
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(v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn),
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(v4i16 V64:$Rm)))))]>;
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(v4i16 V64:$Rm)))))]>;
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def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
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[(set (v8i16 V128:$dst),
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(Accum (v8i16 V128:$Rd),
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@ -9375,28 +9375,28 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
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let Inst{21} = idx{0};
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}
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// FIXME: it would be nice to use the scalar (v1i32) instruction here, but
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// FIXME: it would be nice to use the scalar (v1i32) instruction here, but
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// an intermediate EXTRACT_SUBREG would be untyped.
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// FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we
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// FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we
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// got it lowered here as (i32 vector_extract (v4i32 insert_subvector(..)))
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def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
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(i32 (vector_extract
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(i32 (vector_extract
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(v4i32 (insert_subvector
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(undef),
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(v2i32 (int_aarch64_neon_sqrdmulh
|
||||
(undef),
|
||||
(v2i32 (int_aarch64_neon_sqrdmulh
|
||||
(v2i32 V64:$Rn),
|
||||
(v2i32 (AArch64duplane32
|
||||
(v2i32 (AArch64duplane32
|
||||
(v4i32 V128:$Rm),
|
||||
VectorIndexS:$idx)))),
|
||||
(i32 0))),
|
||||
(i64 0))))),
|
||||
(EXTRACT_SUBREG
|
||||
(v2i32 (!cast<Instruction>(NAME # v2i32_indexed)
|
||||
(v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
|
||||
FPR32Op:$Rd,
|
||||
ssub)),
|
||||
(v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
|
||||
FPR32Op:$Rd,
|
||||
ssub)),
|
||||
V64:$Rn,
|
||||
V128:$Rm,
|
||||
V128:$Rm,
|
||||
VectorIndexS:$idx)),
|
||||
ssub)>;
|
||||
|
||||
@ -9417,26 +9417,26 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
|
||||
// FIXME: it would be nice to use the scalar (v1i32) instruction here, but
|
||||
// an intermediate EXTRACT_SUBREG would be untyped.
|
||||
def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
|
||||
(i32 (vector_extract
|
||||
(v4i32 (int_aarch64_neon_sqrdmulh
|
||||
(i32 (vector_extract
|
||||
(v4i32 (int_aarch64_neon_sqrdmulh
|
||||
(v4i32 V128:$Rn),
|
||||
(v4i32 (AArch64duplane32
|
||||
(v4i32 (AArch64duplane32
|
||||
(v4i32 V128:$Rm),
|
||||
VectorIndexS:$idx)))),
|
||||
(i64 0))))),
|
||||
(EXTRACT_SUBREG
|
||||
(v4i32 (!cast<Instruction>(NAME # v4i32_indexed)
|
||||
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
|
||||
FPR32Op:$Rd,
|
||||
ssub)),
|
||||
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
|
||||
FPR32Op:$Rd,
|
||||
ssub)),
|
||||
V128:$Rn,
|
||||
V128:$Rm,
|
||||
V128:$Rm,
|
||||
VectorIndexS:$idx)),
|
||||
ssub)>;
|
||||
|
||||
def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
|
||||
FPR16Op, FPR16Op, V128_lo,
|
||||
VectorIndexH, asm, ".h", "", "", ".h",
|
||||
VectorIndexH, asm, ".h", "", "", ".h",
|
||||
[]> {
|
||||
bits<3> idx;
|
||||
let Inst{11} = idx{2};
|
||||
@ -9930,7 +9930,7 @@ class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
|
||||
let Predicates = [HasLSE];
|
||||
}
|
||||
|
||||
multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
|
||||
multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
|
||||
string order> {
|
||||
let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
|
||||
def B : BaseLDOPregister<op, order, "b", GPR32>;
|
||||
@ -9947,15 +9947,15 @@ multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel,
|
||||
let Predicates = [HasLSE] in
|
||||
multiclass LDOPregister_patterns_ord_dag<string inst, string suffix, string op,
|
||||
string size, dag SrcRHS, dag DstRHS> {
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS),
|
||||
(!cast<Instruction>(inst # suffix) DstRHS, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS),
|
||||
(!cast<Instruction>(inst # "A" # suffix) DstRHS, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_release") GPR64sp:$Rn, SrcRHS),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_release") GPR64sp:$Rn, SrcRHS),
|
||||
(!cast<Instruction>(inst # "L" # suffix) DstRHS, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS),
|
||||
(!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS),
|
||||
(!cast<Instruction>(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>;
|
||||
}
|
||||
|
||||
@ -9994,15 +9994,15 @@ multiclass LDOPregister_patterns_mod<string inst, string op, string mod> {
|
||||
let Predicates = [HasLSE] in
|
||||
multiclass CASregister_patterns_ord_dag<string inst, string suffix, string op,
|
||||
string size, dag OLD, dag NEW> {
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_monotonic") GPR64sp:$Rn, OLD, NEW),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_monotonic") GPR64sp:$Rn, OLD, NEW),
|
||||
(!cast<Instruction>(inst # suffix) OLD, NEW, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_acquire") GPR64sp:$Rn, OLD, NEW),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_acquire") GPR64sp:$Rn, OLD, NEW),
|
||||
(!cast<Instruction>(inst # "A" # suffix) OLD, NEW, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_release") GPR64sp:$Rn, OLD, NEW),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_release") GPR64sp:$Rn, OLD, NEW),
|
||||
(!cast<Instruction>(inst # "L" # suffix) OLD, NEW, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, OLD, NEW),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_acq_rel") GPR64sp:$Rn, OLD, NEW),
|
||||
(!cast<Instruction>(inst # "AL" # suffix) OLD, NEW, GPR64sp:$Rn)>;
|
||||
def : Pat<(!cast<SDNode>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, OLD, NEW),
|
||||
def : Pat<(!cast<PatFrag>(op#"_"#size#"_seq_cst") GPR64sp:$Rn, OLD, NEW),
|
||||
(!cast<Instruction>(inst # "AL" # suffix) OLD, NEW, GPR64sp:$Rn)>;
|
||||
}
|
||||
|
||||
|
||||
@ -500,7 +500,7 @@ let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
|
||||
|
||||
class SMRD_Pattern_ci <string Instr, ValueType vt> : GCNPat <
|
||||
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
|
||||
(vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
|
||||
(vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
|
||||
let OtherPredicates = [isCIOnly];
|
||||
}
|
||||
|
||||
|
||||
@ -115,13 +115,13 @@ class AddressingMode<string seltype, string bitsize, string dispsize,
|
||||
class BDMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize))>;
|
||||
|
||||
// An addressing mode with a base, displacement and index.
|
||||
class BDXMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<RegisterOperand>("ADDR"##bitsize))>;
|
||||
|
||||
// A BDMode paired with an immediate length operand of LENSIZE bits.
|
||||
@ -130,21 +130,21 @@ class BDLMode<string type, string bitsize, string dispsize, string suffix,
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
|
||||
"BDLAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Immediate>("imm"##bitsize))>;
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Operand>("imm"##bitsize))>;
|
||||
|
||||
// A BDMode paired with a register length operand.
|
||||
class BDRMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<RegisterOperand>("GR"##bitsize))>;
|
||||
|
||||
// An addressing mode with a base, displacement and a vector index.
|
||||
class BDVMode<string bitsize, string dispsize>
|
||||
: AddressOperand<bitsize, dispsize, "", "BDVAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Immediate>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<RegisterOperand>("VR128"))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -10,5 +10,5 @@ class C<string name> {
|
||||
B b = !cast<B>(name);
|
||||
}
|
||||
|
||||
// CHECK: error: Invalid value of type 'A' is found when setting 'b' of type 'B'
|
||||
// CHECK: error: Expected type 'B', got 'A' in: !cast<B>("A0")
|
||||
def Test : C<"A0">;
|
||||
|
||||
@ -16,6 +16,14 @@
|
||||
// CHECK: dag q = (ops C0);
|
||||
// CHECK: }
|
||||
|
||||
// CHECK: def D0 {
|
||||
// CHECK: D d = D0;
|
||||
// CHECK: }
|
||||
|
||||
// CHECK: def E0 {
|
||||
// CHECK: E e = E0;
|
||||
// CHECK: }
|
||||
|
||||
def ops;
|
||||
|
||||
class A<dag d> {
|
||||
@ -42,3 +50,26 @@ class C<string self> {
|
||||
}
|
||||
|
||||
def C0 : C<"C0">;
|
||||
|
||||
// Explore some unused corner cases.
|
||||
//
|
||||
// A self-reference within a class may seem icky, but it unavoidably falls out
|
||||
// orthogonally of having forward class declarations and late resolve of self
|
||||
// references.
|
||||
class D<string self> {
|
||||
D d = !cast<D>(self);
|
||||
}
|
||||
|
||||
def D0 : D<"D0">;
|
||||
|
||||
class E<E x> {
|
||||
E e = x;
|
||||
}
|
||||
|
||||
// Putting the !cast directly in the def should work as well: we shouldn't
|
||||
// depend on implementation details of when exactly the record is looked up.
|
||||
//
|
||||
// Note the difference between !cast<E>("E0") and plain E0: the latter wouldn't
|
||||
// work here because E0 does not yet have E as a superclass while the template
|
||||
// arguments are being parsed.
|
||||
def E0 : E<!cast<E>("E0")>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user