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[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer

Browse Source 
This follows similar logic in the ARM and Mips backends, and allows the free
use of s0 in functions without a dedicated frame pointer. The changes in
callee-saved-gprs.ll most clearly show the effect of this patch.

llvm-svn: 356063
This commit is contained in:
Alex Bradbury 2019-03-13 16:33:45 +00:00
parent 262a0524ce
commit a678d607a6
20 changed files with 2717 additions and 2713 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/RISCV/RISCVRegisterInfo.cpp
View File

@ -43,6 +43,7 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = getFrameLowering(MF);
BitVector Reserved(getNumRegs());
// Use markSuperRegs to ensure any register aliases are also reserved
@ -51,7 +52,8 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::X2); // sp
markSuperRegs(Reserved, RISCV::X3); // gp
markSuperRegs(Reserved, RISCV::X4); // tp
markSuperRegs(Reserved, RISCV::X8); // fp
if (TFI->hasFP(MF))
markSuperRegs(Reserved, RISCV::X8); // fp
assert(checkAllSuperRegsMarked(Reserved));
return Reserved;
}

4800
test/CodeGen/RISCV/atomic-rmw.ll
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File diff suppressed because it is too large Load Diff

88
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View File

@ -257,13 +257,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s1, 24(sp)
; RV32I-NEXT: sw s2, 20(sp)
; RV32I-NEXT: sw s3, 16(sp)
; RV32I-NEXT: sw s4, 12(sp)
; RV32I-NEXT: sw s5, 8(sp)
; RV32I-NEXT: sw s6, 4(sp)
; RV32I-NEXT: sw s7, 0(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1
@ -275,18 +275,18 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s1, a1, 819
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s7, a1, -241
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: addi s1, a1, -241
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0
@ -296,13 +296,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB7_2
@ -314,13 +314,13 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s7, 0(sp)
; RV32I-NEXT: lw s6, 4(sp)
; RV32I-NEXT: lw s5, 8(sp)
; RV32I-NEXT: lw s4, 12(sp)
; RV32I-NEXT: lw s3, 16(sp)
; RV32I-NEXT: lw s2, 20(sp)
; RV32I-NEXT: lw s1, 24(sp)
; RV32I-NEXT: lw s6, 0(sp)
; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
@ -438,13 +438,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s1, 24(sp)
; RV32I-NEXT: sw s2, 20(sp)
; RV32I-NEXT: sw s3, 16(sp)
; RV32I-NEXT: sw s4, 12(sp)
; RV32I-NEXT: sw s5, 8(sp)
; RV32I-NEXT: sw s6, 4(sp)
; RV32I-NEXT: sw s7, 0(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1
@ -456,18 +456,18 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s1, a1, 819
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: addi s0, a1, 819
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s7, a1, -241
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: addi s1, a1, -241
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0
@ -477,13 +477,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s1
; RV32I-NEXT: and a1, a0, s0
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB11_2
@ -495,13 +495,13 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s7, 0(sp)
; RV32I-NEXT: lw s6, 4(sp)
; RV32I-NEXT: lw s5, 8(sp)
; RV32I-NEXT: lw s4, 12(sp)
; RV32I-NEXT: lw s3, 16(sp)
; RV32I-NEXT: lw s2, 20(sp)
; RV32I-NEXT: lw s1, 24(sp)
; RV32I-NEXT: lw s6, 0(sp)
; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret

48
test/CodeGen/RISCV/callee-saved-gprs.ll
View File

@ -9,23 +9,22 @@
@var = global [32 x i32] zeroinitializer
; TODO: s0 need not be reserved if the function doesn't use a framepointer.
define void @foo() {
; RV32I-LABEL: foo:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw s1, 76(sp)
; RV32I-NEXT: sw s2, 72(sp)
; RV32I-NEXT: sw s3, 68(sp)
; RV32I-NEXT: sw s4, 64(sp)
; RV32I-NEXT: sw s5, 60(sp)
; RV32I-NEXT: sw s6, 56(sp)
; RV32I-NEXT: sw s7, 52(sp)
; RV32I-NEXT: sw s8, 48(sp)
; RV32I-NEXT: sw s9, 44(sp)
; RV32I-NEXT: sw s10, 40(sp)
; RV32I-NEXT: sw s11, 36(sp)
; RV32I-NEXT: sw s0, 76(sp)
; RV32I-NEXT: sw s1, 72(sp)
; RV32I-NEXT: sw s2, 68(sp)
; RV32I-NEXT: sw s3, 64(sp)
; RV32I-NEXT: sw s4, 60(sp)
; RV32I-NEXT: sw s5, 56(sp)
; RV32I-NEXT: sw s6, 52(sp)
; RV32I-NEXT: sw s7, 48(sp)
; RV32I-NEXT: sw s8, 44(sp)
; RV32I-NEXT: sw s9, 40(sp)
; RV32I-NEXT: sw s10, 36(sp)
; RV32I-NEXT: sw s11, 32(sp)
; RV32I-NEXT: lui a0, %hi(var)
; RV32I-NEXT: addi a1, a0, %lo(var)
;
@ -52,17 +51,18 @@ define void @foo() {
; RV64I-LABEL: foo:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -144
; RV64I-NEXT: sd s1, 136(sp)
; RV64I-NEXT: sd s2, 128(sp)
; RV64I-NEXT: sd s3, 120(sp)
; RV64I-NEXT: sd s4, 112(sp)
; RV64I-NEXT: sd s5, 104(sp)
; RV64I-NEXT: sd s6, 96(sp)
; RV64I-NEXT: sd s7, 88(sp)
; RV64I-NEXT: sd s8, 80(sp)
; RV64I-NEXT: sd s9, 72(sp)
; RV64I-NEXT: sd s10, 64(sp)
; RV64I-NEXT: sd s11, 56(sp)
; RV64I-NEXT: sd s0, 136(sp)
; RV64I-NEXT: sd s1, 128(sp)
; RV64I-NEXT: sd s2, 120(sp)
; RV64I-NEXT: sd s3, 112(sp)
; RV64I-NEXT: sd s4, 104(sp)
; RV64I-NEXT: sd s5, 96(sp)
; RV64I-NEXT: sd s6, 88(sp)
; RV64I-NEXT: sd s7, 80(sp)
; RV64I-NEXT: sd s8, 72(sp)
; RV64I-NEXT: sd s9, 64(sp)
; RV64I-NEXT: sd s10, 56(sp)
; RV64I-NEXT: sd s11, 48(sp)
; RV64I-NEXT: lui a0, %hi(var)
; RV64I-NEXT: addi a1, a0, %lo(var)
;

8
test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
View File

@ -16,13 +16,13 @@ define i32 @callee_double_in_regs(i32 %a, double %b) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s1, 8(sp)
; RV32I-FPELIM-NEXT: mv s1, a0
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: mv s0, a0
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: mv a1, a2
; RV32I-FPELIM-NEXT: call __fixdfsi
; RV32I-FPELIM-NEXT: add a0, s1, a0
; RV32I-FPELIM-NEXT: lw s1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, s0, a0
; RV32I-FPELIM-NEXT: lw s0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret

8
test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
View File

@ -775,17 +775,17 @@ define i32 @caller_small_scalar_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s1, 8(sp)
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: lui a0, 56
; RV32I-FPELIM-NEXT: addi s1, a0, 580
; RV32I-FPELIM-NEXT: addi s0, a0, 580
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
; RV32I-FPELIM-NEXT: xor a1, a1, s1
; RV32I-FPELIM-NEXT: xor a1, a1, s0
; RV32I-FPELIM-NEXT: lui a2, 200614
; RV32I-FPELIM-NEXT: addi a2, a2, 647
; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: lw s1, 8(sp)
; RV32I-FPELIM-NEXT: lw s0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret

8
test/CodeGen/RISCV/calling-conv-ilp32.ll
View File

@ -17,12 +17,12 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s1, 8(sp)
; RV32I-FPELIM-NEXT: mv s1, a0
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: mv s0, a0
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: call __fixsfsi
; RV32I-FPELIM-NEXT: add a0, s1, a0
; RV32I-FPELIM-NEXT: lw s1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, s0, a0
; RV32I-FPELIM-NEXT: lw s0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret

8
test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
View File

@ -11,12 +11,12 @@ define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd s1, 0(sp)
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: call __fixdfdi
; RV64I-NEXT: add a0, s1, a0
; RV64I-NEXT: ld s1, 0(sp)
; RV64I-NEXT: add a0, s0, a0
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret

8
test/CodeGen/RISCV/calling-conv-lp64.ll
View File

@ -19,13 +19,13 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp)
; RV64I-FPELIM-NEXT: sd s1, 0(sp)
; RV64I-FPELIM-NEXT: mv s1, a0
; RV64I-FPELIM-NEXT: sd s0, 0(sp)
; RV64I-FPELIM-NEXT: mv s0, a0
; RV64I-FPELIM-NEXT: slli a0, a1, 32
; RV64I-FPELIM-NEXT: srli a0, a0, 32
; RV64I-FPELIM-NEXT: call __fixsfdi
; RV64I-FPELIM-NEXT: add a0, s1, a0
; RV64I-FPELIM-NEXT: ld s1, 0(sp)
; RV64I-FPELIM-NEXT: add a0, s0, a0
; RV64I-FPELIM-NEXT: ld s0, 0(sp)
; RV64I-FPELIM-NEXT: ld ra, 8(sp)
; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret

16
test/CodeGen/RISCV/calls.ll
View File

@ -71,11 +71,11 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call fastcc_function
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@ -90,8 +90,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s1, 8(sp)
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a0, 4(sp)
; RV32I-NEXT: sw a0, 0(sp)
; RV32I-NEXT: mv a1, a0
@ -102,8 +102,8 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: call external_many_args
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 8(sp)
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret

44
test/CodeGen/RISCV/double-intrinsics.ll
View File

@ -109,32 +109,32 @@ define double @sincos_f64(double %a) nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s1, 24(sp)
; RV32IFD-NEXT: sw s2, 20(sp)
; RV32IFD-NEXT: sw s3, 16(sp)
; RV32IFD-NEXT: sw s4, 12(sp)
; RV32IFD-NEXT: mv s2, a1
; RV32IFD-NEXT: sw s0, 24(sp)
; RV32IFD-NEXT: sw s1, 20(sp)
; RV32IFD-NEXT: sw s2, 16(sp)
; RV32IFD-NEXT: sw s3, 12(sp)
; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: call sin
; RV32IFD-NEXT: mv s3, a0
; RV32IFD-NEXT: mv s4, a1
; RV32IFD-NEXT: mv s2, a0
; RV32IFD-NEXT: mv s3, a1
; RV32IFD-NEXT: mv a0, s1
; RV32IFD-NEXT: mv a1, s2
; RV32IFD-NEXT: mv a1, s0
; RV32IFD-NEXT: call cos
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw s3, 0(sp)
; RV32IFD-NEXT: sw s4, 4(sp)
; RV32IFD-NEXT: sw s2, 0(sp)
; RV32IFD-NEXT: sw s3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp)
; RV32IFD-NEXT: lw a1, 4(sp)
; RV32IFD-NEXT: lw s4, 12(sp)
; RV32IFD-NEXT: lw s3, 16(sp)
; RV32IFD-NEXT: lw s2, 20(sp)
; RV32IFD-NEXT: lw s1, 24(sp)
; RV32IFD-NEXT: lw s3, 12(sp)
; RV32IFD-NEXT: lw s2, 16(sp)
; RV32IFD-NEXT: lw s1, 20(sp)
; RV32IFD-NEXT: lw s0, 24(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
@ -143,19 +143,19 @@ define double @sincos_f64(double %a) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s1, 16(sp)
; RV64IFD-NEXT: sd s2, 8(sp)
; RV64IFD-NEXT: mv s1, a0
; RV64IFD-NEXT: sd s0, 16(sp)
; RV64IFD-NEXT: sd s1, 8(sp)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: call sin
; RV64IFD-NEXT: mv s2, a0
; RV64IFD-NEXT: mv a0, s1
; RV64IFD-NEXT: mv s1, a0
; RV64IFD-NEXT: mv a0, s0
; RV64IFD-NEXT: call cos
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, s2
; RV64IFD-NEXT: fmv.d.x ft1, s1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s2, 8(sp)
; RV64IFD-NEXT: ld s1, 16(sp)
; RV64IFD-NEXT: ld s1, 8(sp)
; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret

20
test/CodeGen/RISCV/double-mem.ll
View File

@ -159,22 +159,22 @@ define double @fld_stack(double %a) nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s1, 24(sp)
; RV32IFD-NEXT: sw s2, 20(sp)
; RV32IFD-NEXT: mv s2, a1
; RV32IFD-NEXT: sw s0, 24(sp)
; RV32IFD-NEXT: sw s1, 20(sp)
; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: sw s1, 0(sp)
; RV32IFD-NEXT: sw s2, 4(sp)
; RV32IFD-NEXT: sw s0, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp)
; RV32IFD-NEXT: lw a1, 4(sp)
; RV32IFD-NEXT: lw s2, 20(sp)
; RV32IFD-NEXT: lw s1, 24(sp)
; RV32IFD-NEXT: lw s1, 20(sp)
; RV32IFD-NEXT: lw s0, 24(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
@ -183,15 +183,15 @@ define double @fld_stack(double %a) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s1, 16(sp)
; RV64IFD-NEXT: mv s1, a0
; RV64IFD-NEXT: sd s0, 16(sp)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: addi a0, sp, 8
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: fmv.d.x ft0, s1
; RV64IFD-NEXT: fmv.d.x ft0, s0
; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s1, 16(sp)
; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret

10
test/CodeGen/RISCV/float-br-fcmp.ll
View File

@ -754,20 +754,20 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s1, 16(sp)
; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64IF-NEXT: flw ft0, 0(a0)
; RV64IF-NEXT: fsw ft0, 12(sp)
; RV64IF-NEXT: fmv.x.w s1, ft0
; RV64IF-NEXT: mv a0, s1
; RV64IF-NEXT: fmv.x.w s0, ft0
; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call dummy
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: flw ft1, 12(sp)
; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.1: # %if.end
; RV64IF-NEXT: mv a0, s1
; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call dummy
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: flw ft1, 12(sp)
@ -775,7 +775,7 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.2: # %if.end4
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: ld s1, 16(sp)
; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret

32
test/CodeGen/RISCV/float-intrinsics.ll
View File

@ -107,19 +107,19 @@ define float @sincos_f32(float %a) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s1, 8(sp)
; RV32IF-NEXT: sw s2, 4(sp)
; RV32IF-NEXT: mv s1, a0
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw s1, 4(sp)
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: call sinf
; RV32IF-NEXT: mv s2, a0
; RV32IF-NEXT: mv a0, s1
; RV32IF-NEXT: mv s1, a0
; RV32IF-NEXT: mv a0, s0
; RV32IF-NEXT: call cosf
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, s2
; RV32IF-NEXT: fmv.w.x ft1, s1
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s2, 4(sp)
; RV32IF-NEXT: lw s1, 8(sp)
; RV32IF-NEXT: lw s1, 4(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@ -128,19 +128,19 @@ define float @sincos_f32(float %a) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s1, 16(sp)
; RV64IF-NEXT: sd s2, 8(sp)
; RV64IF-NEXT: mv s1, a0
; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: sd s1, 8(sp)
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: call sinf
; RV64IF-NEXT: mv s2, a0
; RV64IF-NEXT: mv a0, s1
; RV64IF-NEXT: mv s1, a0
; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call cosf
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, s2
; RV64IF-NEXT: fmv.w.x ft1, s1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s2, 8(sp)
; RV64IF-NEXT: ld s1, 16(sp)
; RV64IF-NEXT: ld s1, 8(sp)
; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret

16
test/CodeGen/RISCV/float-mem.ll
View File

@ -135,15 +135,15 @@ define float @flw_stack(float %a) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s1, 8(sp)
; RV32IF-NEXT: mv s1, a0
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: addi a0, sp, 4
; RV32IF-NEXT: call notdead
; RV32IF-NEXT: fmv.w.x ft0, s1
; RV32IF-NEXT: fmv.w.x ft0, s0
; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s1, 8(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@ -152,15 +152,15 @@ define float @flw_stack(float %a) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s1, 16(sp)
; RV64IF-NEXT: mv s1, a0
; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: addi a0, sp, 12
; RV64IF-NEXT: call notdead
; RV64IF-NEXT: fmv.w.x ft0, s1
; RV64IF-NEXT: fmv.w.x ft0, s0
; RV64IF-NEXT: flw ft1, 12(sp)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s1, 16(sp)
; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret

8
test/CodeGen/RISCV/large-stack.ll
View File

@ -61,11 +61,11 @@ define void @test_emergency_spill_slot(i32 %a) nounwind {
; RV32I-FPELIM-NEXT: lui a1, 98
; RV32I-FPELIM-NEXT: addi a1, a1, -1396
; RV32I-FPELIM-NEXT: add a1, sp, a1
; RV32I-FPELIM-NEXT: sw s1, 0(a1)
; RV32I-FPELIM-NEXT: sw s0, 0(a1)
; RV32I-FPELIM-NEXT: lui a1, 98
; RV32I-FPELIM-NEXT: addi a1, a1, -1400
; RV32I-FPELIM-NEXT: add a1, sp, a1
; RV32I-FPELIM-NEXT: sw s2, 0(a1)
; RV32I-FPELIM-NEXT: sw s1, 0(a1)
; RV32I-FPELIM-NEXT: lui a1, 78
; RV32I-FPELIM-NEXT: addi a1, a1, 512
; RV32I-FPELIM-NEXT: addi a2, sp, 8
@ -80,11 +80,11 @@ define void @test_emergency_spill_slot(i32 %a) nounwind {
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1400
; RV32I-FPELIM-NEXT: add a0, sp, a0
; RV32I-FPELIM-NEXT: lw s2, 0(a0)
; RV32I-FPELIM-NEXT: lw s1, 0(a0)
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1396
; RV32I-FPELIM-NEXT: add a0, sp, a0
; RV32I-FPELIM-NEXT: lw s1, 0(a0)
; RV32I-FPELIM-NEXT: lw s0, 0(a0)
; RV32I-FPELIM-NEXT: lui a0, 98
; RV32I-FPELIM-NEXT: addi a0, a0, -1392
; RV32I-FPELIM-NEXT: add sp, sp, a0

96
test/CodeGen/RISCV/remat.ll
View File

@ -23,19 +23,20 @@
define i32 @test() nounwind {
; RV32I-LABEL: test:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s1, 40(sp)
; RV32I-NEXT: sw s2, 36(sp)
; RV32I-NEXT: sw s3, 32(sp)
; RV32I-NEXT: sw s4, 28(sp)
; RV32I-NEXT: sw s5, 24(sp)
; RV32I-NEXT: sw s6, 20(sp)
; RV32I-NEXT: sw s7, 16(sp)
; RV32I-NEXT: sw s8, 12(sp)
; RV32I-NEXT: sw s9, 8(sp)
; RV32I-NEXT: sw s10, 4(sp)
; RV32I-NEXT: sw s11, 0(sp)
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp)
; RV32I-NEXT: sw s0, 56(sp)
; RV32I-NEXT: sw s1, 52(sp)
; RV32I-NEXT: sw s2, 48(sp)
; RV32I-NEXT: sw s3, 44(sp)
; RV32I-NEXT: sw s4, 40(sp)
; RV32I-NEXT: sw s5, 36(sp)
; RV32I-NEXT: sw s6, 32(sp)
; RV32I-NEXT: sw s7, 28(sp)
; RV32I-NEXT: sw s8, 24(sp)
; RV32I-NEXT: sw s9, 20(sp)
; RV32I-NEXT: sw s10, 16(sp)
; RV32I-NEXT: sw s11, 12(sp)
; RV32I-NEXT: lui s9, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s9)
; RV32I-NEXT: beqz a0, .LBB0_11
@ -43,23 +44,24 @@ define i32 @test() nounwind {
; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s5, %hi(i)
; RV32I-NEXT: lui s6, %hi(i)
; RV32I-NEXT: lui s5, %hi(h)
; RV32I-NEXT: lui s7, %hi(g)
; RV32I-NEXT: lui s8, %hi(f)
; RV32I-NEXT: lui s10, %hi(e)
; RV32I-NEXT: lui s1, %hi(d)
; RV32I-NEXT: lui s11, %hi(c)
; RV32I-NEXT: lui s6, %hi(b)
; RV32I-NEXT: lui s1, %hi(e)
; RV32I-NEXT: lui s0, %hi(d)
; RV32I-NEXT: lui s10, %hi(c)
; RV32I-NEXT: lui s11, %hi(b)
; RV32I-NEXT: .LBB0_2: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: beqz a1, .LBB0_4
; RV32I-NEXT: # %bb.3: # %if.then
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(e)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(c)(s11)
; RV32I-NEXT: lw a1, %lo(b)(s6)
; RV32I-NEXT: lw a4, %lo(e)(s1)
; RV32I-NEXT: lw a3, %lo(d)(s0)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_4: # %if.end
@ -69,10 +71,10 @@ define i32 @test() nounwind {
; RV32I-NEXT: # %bb.5: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(f)(s8)
; RV32I-NEXT: lw a3, %lo(e)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(c)(s11)
; RV32I-NEXT: lw a0, %lo(b)(s6)
; RV32I-NEXT: lw a3, %lo(e)(s1)
; RV32I-NEXT: lw a2, %lo(d)(s0)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_6: # %if.end5
@ -83,23 +85,22 @@ define i32 @test() nounwind {
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(g)(s7)
; RV32I-NEXT: lw a3, %lo(f)(s8)
; RV32I-NEXT: lw a2, %lo(e)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a0, %lo(c)(s11)
; RV32I-NEXT: lw a2, %lo(e)(s1)
; RV32I-NEXT: lw a1, %lo(d)(s0)
; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_8: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: lw a0, %lo(i)(s6)
; RV32I-NEXT: beqz a0, .LBB0_10
; RV32I-NEXT: # %bb.9: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lui a0, %hi(h)
; RV32I-NEXT: lw a4, %lo(h)(a0)
; RV32I-NEXT: lw a4, %lo(h)(s5)
; RV32I-NEXT: lw a3, %lo(g)(s7)
; RV32I-NEXT: lw a2, %lo(f)(s8)
; RV32I-NEXT: lw a1, %lo(e)(s10)
; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(e)(s1)
; RV32I-NEXT: lw a0, %lo(d)(s0)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_10: # %for.inc
@ -110,19 +111,20 @@ define i32 @test() nounwind {
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: lw s11, 0(sp)
; RV32I-NEXT: lw s10, 4(sp)
; RV32I-NEXT: lw s9, 8(sp)
; RV32I-NEXT: lw s8, 12(sp)
; RV32I-NEXT: lw s7, 16(sp)
; RV32I-NEXT: lw s6, 20(sp)
; RV32I-NEXT: lw s5, 24(sp)
; RV32I-NEXT: lw s4, 28(sp)
; RV32I-NEXT: lw s3, 32(sp)
; RV32I-NEXT: lw s2, 36(sp)
; RV32I-NEXT: lw s1, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: lw s11, 12(sp)
; RV32I-NEXT: lw s10, 16(sp)
; RV32I-NEXT: lw s9, 20(sp)
; RV32I-NEXT: lw s8, 24(sp)
; RV32I-NEXT: lw s7, 28(sp)
; RV32I-NEXT: lw s6, 32(sp)
; RV32I-NEXT: lw s5, 36(sp)
; RV32I-NEXT: lw s4, 40(sp)
; RV32I-NEXT: lw s3, 44(sp)
; RV32I-NEXT: lw s2, 48(sp)
; RV32I-NEXT: lw s1, 52(sp)
; RV32I-NEXT: lw s0, 56(sp)
; RV32I-NEXT: lw ra, 60(sp)
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
entry:
%.pr = load i32, i32* @a, align 4

38
test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
View File

@ -16,12 +16,12 @@ define float @float_test(float %a, float %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s1, 8(sp)
; RV32IF-NEXT: mv s1, a1
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: mv s0, a1
; RV32IF-NEXT: call __addsf3
; RV32IF-NEXT: mv a1, s1
; RV32IF-NEXT: mv a1, s0
; RV32IF-NEXT: call __divsf3
; RV32IF-NEXT: lw s1, 8(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@ -30,16 +30,16 @@ define float @float_test(float %a, float %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd s1, 0(sp)
; RV64IF-NEXT: sd s0, 0(sp)
; RV64IF-NEXT: slli a0, a0, 32
; RV64IF-NEXT: srli a0, a0, 32
; RV64IF-NEXT: slli a1, a1, 32
; RV64IF-NEXT: srli s1, a1, 32
; RV64IF-NEXT: mv a1, s1
; RV64IF-NEXT: srli s0, a1, 32
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __addsf3
; RV64IF-NEXT: mv a1, s1
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divsf3
; RV64IF-NEXT: ld s1, 0(sp)
; RV64IF-NEXT: ld s0, 0(sp)
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
@ -53,16 +53,16 @@ define double @double_test(double %a, double %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s1, 8(sp)
; RV32IF-NEXT: sw s2, 4(sp)
; RV32IF-NEXT: mv s2, a3
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw s1, 4(sp)
; RV32IF-NEXT: mv s0, a3
; RV32IF-NEXT: mv s1, a2
; RV32IF-NEXT: call __adddf3
; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: mv a3, s2
; RV32IF-NEXT: mv a3, s0
; RV32IF-NEXT: call __divdf3
; RV32IF-NEXT: lw s2, 4(sp)
; RV32IF-NEXT: lw s1, 8(sp)
; RV32IF-NEXT: lw s1, 4(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
@ -71,12 +71,12 @@ define double @double_test(double %a, double %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd s1, 0(sp)
; RV64IF-NEXT: mv s1, a1
; RV64IF-NEXT: sd s0, 0(sp)
; RV64IF-NEXT: mv s0, a1
; RV64IF-NEXT: call __adddf3
; RV64IF-NEXT: mv a1, s1
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divdf3
; RV64IF-NEXT: ld s1, 0(sp)
; RV64IF-NEXT: ld s0, 0(sp)
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret

162
test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
View File

@ -6,107 +6,107 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; RISCV32: # %bb.0: # %start
; RISCV32-NEXT: addi sp, sp, -80
; RISCV32-NEXT: sw ra, 76(sp)
; RISCV32-NEXT: sw s1, 72(sp)
; RISCV32-NEXT: sw s2, 68(sp)
; RISCV32-NEXT: sw s3, 64(sp)
; RISCV32-NEXT: sw s4, 60(sp)
; RISCV32-NEXT: sw s5, 56(sp)
; RISCV32-NEXT: sw s6, 52(sp)
; RISCV32-NEXT: sw s7, 48(sp)
; RISCV32-NEXT: mv s3, a2
; RISCV32-NEXT: mv s1, a1
; RISCV32-NEXT: sw s0, 72(sp)
; RISCV32-NEXT: sw s1, 68(sp)
; RISCV32-NEXT: sw s2, 64(sp)
; RISCV32-NEXT: sw s3, 60(sp)
; RISCV32-NEXT: sw s4, 56(sp)
; RISCV32-NEXT: sw s5, 52(sp)
; RISCV32-NEXT: sw s6, 48(sp)
; RISCV32-NEXT: mv s1, a2
; RISCV32-NEXT: mv s0, a1
; RISCV32-NEXT: mv s2, a0
; RISCV32-NEXT: sw zero, 12(sp)
; RISCV32-NEXT: sw zero, 8(sp)
; RISCV32-NEXT: sw zero, 28(sp)
; RISCV32-NEXT: sw zero, 24(sp)
; RISCV32-NEXT: lw s4, 4(a2)
; RISCV32-NEXT: sw s4, 4(sp)
; RISCV32-NEXT: lw s6, 0(a2)
; RISCV32-NEXT: sw s6, 0(sp)
; RISCV32-NEXT: lw s5, 4(a1)
; RISCV32-NEXT: sw s5, 20(sp)
; RISCV32-NEXT: lw s7, 0(a1)
; RISCV32-NEXT: sw s7, 16(sp)
; RISCV32-NEXT: lw s3, 4(a2)
; RISCV32-NEXT: sw s3, 4(sp)
; RISCV32-NEXT: lw s5, 0(a2)
; RISCV32-NEXT: sw s5, 0(sp)
; RISCV32-NEXT: lw s4, 4(a1)
; RISCV32-NEXT: sw s4, 20(sp)
; RISCV32-NEXT: lw s6, 0(a1)
; RISCV32-NEXT: sw s6, 16(sp)
; RISCV32-NEXT: addi a0, sp, 32
; RISCV32-NEXT: addi a1, sp, 16
; RISCV32-NEXT: mv a2, sp
; RISCV32-NEXT: call __multi3
; RISCV32-NEXT: lw t4, 12(s1)
; RISCV32-NEXT: lw a1, 8(s1)
; RISCV32-NEXT: mul a2, s4, a1
; RISCV32-NEXT: mul a3, t4, s6
; RISCV32-NEXT: add a7, a3, a2
; RISCV32-NEXT: lw a2, 12(s3)
; RISCV32-NEXT: lw a3, 8(s3)
; RISCV32-NEXT: mul a5, s5, a3
; RISCV32-NEXT: mul s1, a2, s7
; RISCV32-NEXT: lw a0, 12(s0)
; RISCV32-NEXT: lw a1, 8(s0)
; RISCV32-NEXT: mul a2, s3, a1
; RISCV32-NEXT: mul a3, a0, s5
; RISCV32-NEXT: add a4, a3, a2
; RISCV32-NEXT: lw a2, 12(s1)
; RISCV32-NEXT: lw a3, 8(s1)
; RISCV32-NEXT: mul a5, s4, a3
; RISCV32-NEXT: mul s1, a2, s6
; RISCV32-NEXT: add a5, s1, a5
; RISCV32-NEXT: mul s1, a3, s7
; RISCV32-NEXT: mul a4, a1, s6
; RISCV32-NEXT: add s1, a4, s1
; RISCV32-NEXT: sltu a4, s1, a4
; RISCV32-NEXT: mulhu a6, a3, s7
; RISCV32-NEXT: mul s1, a3, s6
; RISCV32-NEXT: mul s0, a1, s5
; RISCV32-NEXT: add s1, s0, s1
; RISCV32-NEXT: sltu s0, s1, s0
; RISCV32-NEXT: mulhu a6, a3, s6
; RISCV32-NEXT: add t1, a6, a5
; RISCV32-NEXT: mulhu t2, a1, s6
; RISCV32-NEXT: add t3, t2, a7
; RISCV32-NEXT: mulhu t2, a1, s5
; RISCV32-NEXT: add t3, t2, a4
; RISCV32-NEXT: add a5, t3, t1
; RISCV32-NEXT: add a5, a5, a4
; RISCV32-NEXT: lw a4, 44(sp)
; RISCV32-NEXT: add a5, a4, a5
; RISCV32-NEXT: lw a0, 40(sp)
; RISCV32-NEXT: add a7, a0, s1
; RISCV32-NEXT: sltu t0, a7, a0
; RISCV32-NEXT: add s1, a5, t0
; RISCV32-NEXT: beq s1, a4, .LBB0_2
; RISCV32-NEXT: add a5, a5, s0
; RISCV32-NEXT: lw s0, 44(sp)
; RISCV32-NEXT: add a5, s0, a5
; RISCV32-NEXT: lw a4, 40(sp)
; RISCV32-NEXT: add a7, a4, s1
; RISCV32-NEXT: sltu t0, a7, a4
; RISCV32-NEXT: add a5, a5, t0
; RISCV32-NEXT: beq a5, s0, .LBB0_2
; RISCV32-NEXT: # %bb.1: # %start
; RISCV32-NEXT: sltu t0, s1, a4
; RISCV32-NEXT: sltu t0, a5, s0
; RISCV32-NEXT: .LBB0_2: # %start
; RISCV32-NEXT: snez a0, s4
; RISCV32-NEXT: snez a4, t4
; RISCV32-NEXT: and a0, a4, a0
; RISCV32-NEXT: snez a4, s5
; RISCV32-NEXT: snez a5, a2
; RISCV32-NEXT: and a4, a5, a4
; RISCV32-NEXT: mulhu a5, a2, s7
; RISCV32-NEXT: snez a5, a5
; RISCV32-NEXT: or a4, a4, a5
; RISCV32-NEXT: mulhu a5, t4, s6
; RISCV32-NEXT: snez a5, a5
; RISCV32-NEXT: or a0, a0, a5
; RISCV32-NEXT: snez a4, s3
; RISCV32-NEXT: snez s1, a0
; RISCV32-NEXT: and a4, s1, a4
; RISCV32-NEXT: snez s1, s4
; RISCV32-NEXT: snez s0, a2
; RISCV32-NEXT: and s1, s0, s1
; RISCV32-NEXT: mulhu s0, a2, s6
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or s1, s1, s0
; RISCV32-NEXT: mulhu s0, a0, s5
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or a4, a4, s0
; RISCV32-NEXT: sltu t2, t3, t2
; RISCV32-NEXT: mulhu a5, s4, a1
; RISCV32-NEXT: snez a5, a5
; RISCV32-NEXT: or t3, a0, a5
; RISCV32-NEXT: sltu a5, t1, a6
; RISCV32-NEXT: mulhu a0, s5, a3
; RISCV32-NEXT: snez a0, a0
; RISCV32-NEXT: or a0, a4, a0
; RISCV32-NEXT: lw a4, 36(sp)
; RISCV32-NEXT: sw a4, 4(s2)
; RISCV32-NEXT: lw a4, 32(sp)
; RISCV32-NEXT: sw a4, 0(s2)
; RISCV32-NEXT: mulhu s0, s3, a1
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or t3, a4, s0
; RISCV32-NEXT: sltu s0, t1, a6
; RISCV32-NEXT: mulhu a4, s4, a3
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a4, s1, a4
; RISCV32-NEXT: lw s1, 36(sp)
; RISCV32-NEXT: sw s1, 4(s2)
; RISCV32-NEXT: lw s1, 32(sp)
; RISCV32-NEXT: sw s1, 0(s2)
; RISCV32-NEXT: sw a7, 8(s2)
; RISCV32-NEXT: sw s1, 12(s2)
; RISCV32-NEXT: or a0, a0, a5
; RISCV32-NEXT: or a4, t3, t2
; RISCV32-NEXT: or a1, a1, t4
; RISCV32-NEXT: or a2, a3, a2
; RISCV32-NEXT: snez a2, a2
; RISCV32-NEXT: snez a1, a1
; RISCV32-NEXT: and a1, a1, a2
; RISCV32-NEXT: or a1, a1, a4
; RISCV32-NEXT: sw a5, 12(s2)
; RISCV32-NEXT: or a4, a4, s0
; RISCV32-NEXT: or a5, t3, t2
; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: or a1, a3, a2
; RISCV32-NEXT: snez a1, a1
; RISCV32-NEXT: snez a0, a0
; RISCV32-NEXT: and a0, a0, a1
; RISCV32-NEXT: or a0, a0, a5
; RISCV32-NEXT: or a0, a0, a4
; RISCV32-NEXT: or a0, a0, t0
; RISCV32-NEXT: andi a0, a0, 1
; RISCV32-NEXT: sb a0, 16(s2)
; RISCV32-NEXT: lw s7, 48(sp)
; RISCV32-NEXT: lw s6, 52(sp)
; RISCV32-NEXT: lw s5, 56(sp)
; RISCV32-NEXT: lw s4, 60(sp)
; RISCV32-NEXT: lw s3, 64(sp)
; RISCV32-NEXT: lw s2, 68(sp)
; RISCV32-NEXT: lw s1, 72(sp)
; RISCV32-NEXT: lw s6, 48(sp)
; RISCV32-NEXT: lw s5, 52(sp)
; RISCV32-NEXT: lw s4, 56(sp)
; RISCV32-NEXT: lw s3, 60(sp)
; RISCV32-NEXT: lw s2, 64(sp)
; RISCV32-NEXT: lw s1, 68(sp)
; RISCV32-NEXT: lw s0, 72(sp)
; RISCV32-NEXT: lw ra, 76(sp)
; RISCV32-NEXT: addi sp, sp, 80
; RISCV32-NEXT: ret

8
test/CodeGen/RISCV/vararg.ll
View File

@ -534,8 +534,8 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s1, 8(sp)
; RV32I-FPELIM-NEXT: mv s1, a1
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: mv s0, a1
; RV32I-FPELIM-NEXT: sw a7, 44(sp)
; RV32I-FPELIM-NEXT: sw a6, 40(sp)
; RV32I-FPELIM-NEXT: sw a5, 36(sp)
@ -562,11 +562,11 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; RV32I-FPELIM-NEXT: andi a0, a0, -4
; RV32I-FPELIM-NEXT: addi a3, a0, 4
; RV32I-FPELIM-NEXT: sw a3, 4(sp)
; RV32I-FPELIM-NEXT: add a1, a1, s1
; RV32I-FPELIM-NEXT: add a1, a1, s0
; RV32I-FPELIM-NEXT: add a1, a1, a2
; RV32I-FPELIM-NEXT: lw a0, 0(a0)
; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: lw s1, 8(sp)
; RV32I-FPELIM-NEXT: lw s0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret