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ARM: remove now unneeded custom Asm converters

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After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

llvm-svn: 186810
This commit is contained in:
Tim Northover 2013-07-22 09:06:12 +00:00
parent 30d02185df
commit a6d63d6cc9
4 changed files with 16 additions and 415 deletions
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12
lib/Target/ARM/ARMInstrInfo.td
View File

@ -2293,7 +2293,6 @@ multiclass AI2_ldridx<bit isByte, string opc,
let Inst{19-16} = addr{16-13}; let Inst{19-16} = addr{16-13};
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
let DecoderMethod = "DecodeLDRPreImm"; let DecoderMethod = "DecodeLDRPreImm";
let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
} }
def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
@ -2306,7 +2305,6 @@ multiclass AI2_ldridx<bit isByte, string opc,
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
let Inst{4} = 0; let Inst{4} = 0;
let DecoderMethod = "DecodeLDRPreReg"; let DecoderMethod = "DecodeLDRPreReg";
let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
} }
def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
@ -2364,7 +2362,6 @@ multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
let Inst{19-16} = addr{12-9}; // Rn let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
let DecoderMethod = "DecodeAddrMode3Instruction"; let DecoderMethod = "DecodeAddrMode3Instruction";
} }
def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
@ -2400,7 +2397,6 @@ def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction"; let DecoderMethod = "DecodeAddrMode3Instruction";
let AsmMatchConverter = "cvtLdrdPre";
} }
def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am3offset:$offset), (ins addr_offset_none:$addr, am3offset:$offset),
@ -2503,7 +2499,6 @@ multiclass AI3ldrT<bits<4> op, string opc> {
let Inst{22} = 1; let Inst{22} = 1;
let Inst{11-8} = offset{7-4}; let Inst{11-8} = offset{7-4};
let Inst{3-0} = offset{3-0}; let Inst{3-0} = offset{3-0};
let AsmMatchConverter = "cvtLdExtTWriteBackImm";
} }
def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
(ins addr_offset_none:$addr, postidx_reg:$Rm), (ins addr_offset_none:$addr, postidx_reg:$Rm),
@ -2515,7 +2510,6 @@ multiclass AI3ldrT<bits<4> op, string opc> {
let Inst{11-8} = 0; let Inst{11-8} = 0;
let Unpredictable{11-8} = 0b1111; let Unpredictable{11-8} = 0b1111;
let Inst{3-0} = Rm{3-0}; let Inst{3-0} = Rm{3-0};
let AsmMatchConverter = "cvtLdExtTWriteBackReg";
let DecoderMethod = "DecodeLDR"; let DecoderMethod = "DecodeLDR";
} }
} }
@ -2553,7 +2547,6 @@ multiclass AI2_stridx<bit isByte, string opc,
let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; // imm12 let Inst{11-0} = addr{11-0}; // imm12
let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
let DecoderMethod = "DecodeSTRPreImm"; let DecoderMethod = "DecodeSTRPreImm";
} }
@ -2567,7 +2560,6 @@ multiclass AI2_stridx<bit isByte, string opc,
let Inst{19-16} = addr{16-13}; // Rn let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
let Inst{4} = 0; // Inst{4} = 0 let Inst{4} = 0; // Inst{4} = 0
let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
let DecoderMethod = "DecodeSTRPreReg"; let DecoderMethod = "DecodeSTRPreReg";
} }
def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
@ -2676,7 +2668,6 @@ def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
let Inst{19-16} = addr{12-9}; // Rn let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
let DecoderMethod = "DecodeAddrMode3Instruction"; let DecoderMethod = "DecodeAddrMode3Instruction";
} }
@ -2710,7 +2701,6 @@ def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm let Inst{3-0} = addr{3-0}; // imm3_0/Rm
let DecoderMethod = "DecodeAddrMode3Instruction"; let DecoderMethod = "DecodeAddrMode3Instruction";
let AsmMatchConverter = "cvtStrdPre";
} }
def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
@ -2817,7 +2807,6 @@ multiclass AI3strT<bits<4> op, string opc> {
let Inst{22} = 1; let Inst{22} = 1;
let Inst{11-8} = offset{7-4}; let Inst{11-8} = offset{7-4};
let Inst{3-0} = offset{3-0}; let Inst{3-0} = offset{3-0};
let AsmMatchConverter = "cvtStExtTWriteBackImm";
} }
def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
(ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
@ -2828,7 +2817,6 @@ multiclass AI3strT<bits<4> op, string opc> {
let Inst{22} = 0; let Inst{22} = 0;
let Inst{11-8} = 0; let Inst{11-8} = 0;
let Inst{3-0} = Rm{3-0}; let Inst{3-0} = Rm{3-0};
let AsmMatchConverter = "cvtStExtTWriteBackReg";
} }
} }

28
lib/Target/ARM/ARMInstrNEON.td
View File

@ -656,7 +656,6 @@ multiclass VLD1DWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u, (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
@ -664,7 +663,6 @@ multiclass VLD1DWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
multiclass VLD1QWB<bits<4> op7_4, string Dt> { multiclass VLD1QWB<bits<4> op7_4, string Dt> {
@ -675,7 +673,6 @@ multiclass VLD1QWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb), def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
@ -683,7 +680,6 @@ multiclass VLD1QWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -713,7 +709,6 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb), def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
@ -721,7 +716,6 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -754,7 +748,6 @@ multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb), def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
@ -762,7 +755,6 @@ multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -811,7 +803,6 @@ multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm), itin, (ins addrmode6:$Rn, rGPR:$Rm), itin,
@ -819,7 +810,6 @@ multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -1348,7 +1338,6 @@ multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD1DupInstruction"; let DecoderMethod = "DecodeVLD1DupInstruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<1, 0b10, 0b1100, op7_4, def _register : NLdSt<1, 0b10, 0b1100, op7_4,
(outs VecListOneDAllLanes:$Vd, GPR:$wb), (outs VecListOneDAllLanes:$Vd, GPR:$wb),
@ -1357,7 +1346,6 @@ multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD1DupInstruction"; let DecoderMethod = "DecodeVLD1DupInstruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> { multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
@ -1369,7 +1357,6 @@ multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD1DupInstruction"; let DecoderMethod = "DecodeVLD1DupInstruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<1, 0b10, 0b1100, op7_4, def _register : NLdSt<1, 0b10, 0b1100, op7_4,
(outs VecListDPairAllLanes:$Vd, GPR:$wb), (outs VecListDPairAllLanes:$Vd, GPR:$wb),
@ -1378,7 +1365,6 @@ multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD1DupInstruction"; let DecoderMethod = "DecodeVLD1DupInstruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -1419,7 +1405,6 @@ multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD2DupInstruction"; let DecoderMethod = "DecodeVLD2DupInstruction";
let AsmMatchConverter = "cvtVLDwbFixed";
} }
def _register : NLdSt<1, 0b10, 0b1101, op7_4, def _register : NLdSt<1, 0b10, 0b1101, op7_4,
(outs VdTy:$Vd, GPR:$wb), (outs VdTy:$Vd, GPR:$wb),
@ -1428,7 +1413,6 @@ multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLD2DupInstruction"; let DecoderMethod = "DecodeVLD2DupInstruction";
let AsmMatchConverter = "cvtVLDwbRegister";
} }
} }
@ -1609,7 +1593,6 @@ multiclass VST1DWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb), def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd), (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
@ -1618,7 +1601,6 @@ multiclass VST1DWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }
multiclass VST1QWB<bits<4> op7_4, string Dt> { multiclass VST1QWB<bits<4> op7_4, string Dt> {
@ -1629,7 +1611,6 @@ multiclass VST1QWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd), (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
@ -1638,7 +1619,6 @@ multiclass VST1QWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }
@ -1669,7 +1649,6 @@ multiclass VST1D3WB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd), (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
@ -1678,7 +1657,6 @@ multiclass VST1D3WB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }
@ -1714,7 +1692,6 @@ multiclass VST1D4WB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
@ -1723,7 +1700,6 @@ multiclass VST1D4WB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST1Instruction"; let DecoderMethod = "DecodeVLDST1Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }
@ -1773,7 +1749,6 @@ multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u, (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
@ -1781,7 +1756,6 @@ multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }
multiclass VST2QWB<bits<4> op7_4, string Dt> { multiclass VST2QWB<bits<4> op7_4, string Dt> {
@ -1792,7 +1766,6 @@ multiclass VST2QWB<bits<4> op7_4, string Dt> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbFixed";
} }
def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
@ -1801,7 +1774,6 @@ multiclass VST2QWB<bits<4> op7_4, string Dt> {
"$Rn.addr = $wb", []> { "$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4}; let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDST2Instruction"; let DecoderMethod = "DecodeVLDST2Instruction";
let AsmMatchConverter = "cvtVSTwbRegister";
} }
} }

42
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1318,10 +1318,7 @@ let mayLoad = 1, neverHasSideEffects = 1 in {
def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr), (ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
[]> {
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
}
def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
@ -1331,10 +1328,8 @@ def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr), (ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
[]> {
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
}
def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
@ -1343,10 +1338,8 @@ def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr), (ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
[]> {
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
}
def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
@ -1356,9 +1349,8 @@ def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr), (ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
[]> { []>;
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
}
def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
@ -1368,9 +1360,8 @@ def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8_pre:$addr), (ins t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
[]> { []>;
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
}
def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
@ -1426,24 +1417,19 @@ def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
(ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr), (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_iu, AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
"str", "\t$Rt, $addr!", "str", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
}
def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_iu, AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
"strh", "\t$Rt, $addr!", "strh", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
}
def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
"strb", "\t$Rt, $addr!", "strb", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
}
} // mayStore = 1, neverHasSideEffects = 1 } // mayStore = 1, neverHasSideEffects = 1
def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
@ -1532,7 +1518,6 @@ def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
(ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru, (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> { "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
let AsmMatchConverter = "cvtT2LdrdPre";
let DecoderMethod = "DecodeT2LDRDPreInstruction"; let DecoderMethod = "DecodeT2LDRDPreInstruction";
} }
@ -1545,7 +1530,6 @@ def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr), (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
"$addr.base = $wb", []> { "$addr.base = $wb", []> {
let AsmMatchConverter = "cvtT2StrdPre";
let DecoderMethod = "DecodeT2STRDPreInstruction"; let DecoderMethod = "DecodeT2STRDPreInstruction";
} }

349
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -219,44 +219,8 @@ class ARMAsmParser : public MCTargetAsmParser {
SMLoc &EndLoc); SMLoc &EndLoc);
// Asm Match Converter Methods // Asm Match Converter Methods
void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStWriteBackRegAddrMode2(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStWriteBackRegAddrMode3(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdExtTWriteBackImm(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdExtTWriteBackReg(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStExtTWriteBackImm(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStExtTWriteBackReg(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtThumbMultiply(MCInst &Inst, void cvtThumbMultiply(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &); const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtVLDwbFixed(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtVLDwbRegister(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtVSTwbFixed(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
void cvtVSTwbRegister(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool validateInstruction(MCInst &Inst, bool validateInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops); const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
bool processInstruction(MCInst &Inst, bool processInstruction(MCInst &Inst,
@ -4077,260 +4041,9 @@ parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_Success; return MatchOperand_Success;
} }
/// cvtT2LdrdPre - Convert parsed operands to MCInst. /// Convert parsed operands to MCInst. Needed here because this instruction
/// Needed here because the Asm Gen Matcher can't handle properly tied operands /// only has two register operands, but multiplication is commutative so
/// when they refer multiple MIOperands inside a single one. /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
void ARMAsmParser::
cvtT2LdrdPre(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Rt, Rt2
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateReg(0));
// addr
((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtT2StrdPre - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtT2StrdPre(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateReg(0));
// Rt, Rt2
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
// addr
((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdWriteBackRegAddrMode2(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStWriteBackRegAddrMode2(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStWriteBackRegAddrMode3(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdExtTWriteBackImm(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Rt
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// addr
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
// offset
((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdExtTWriteBackReg(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Rt
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// addr
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
// offset
((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStExtTWriteBackImm(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Rt
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// addr
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
// offset
((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStExtTWriteBackReg(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Rt
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// addr
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
// offset
((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdrdPre - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdrdPre(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Rt, Rt2
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// addr
((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtStrdPre - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtStrdPre(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Rt, Rt2
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
// addr
((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser::
cvtLdWriteBackRegAddrMode3(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// cvtThumbMultiply - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
void ARMAsmParser:: void ARMAsmParser::
cvtThumbMultiply(MCInst &Inst, cvtThumbMultiply(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
@ -4348,62 +4061,6 @@ cvtThumbMultiply(MCInst &Inst,
((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
} }
void ARMAsmParser::
cvtVLDwbFixed(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Vd
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
void ARMAsmParser::
cvtVLDwbRegister(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Vd
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
// Vm
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
void ARMAsmParser::
cvtVSTwbFixed(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
// Vt
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
void ARMAsmParser::
cvtVSTwbRegister(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
// Vm
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
// Vt
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
}
/// Parse an ARM memory expression, return false if successful else return true /// Parse an ARM memory expression, return false if successful else return true
/// or an error. The first token must be a '[' when called. /// or an error. The first token must be a '[' when called.
bool ARMAsmParser:: bool ARMAsmParser::