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Assembly parsing for 2-register sequential variant of VLD2.

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llvm-svn: 142691
This commit is contained in:
Jim Grosbach 2011-10-21 22:21:10 +00:00
parent 34a9073d67
commit a6e536367e
6 changed files with 54 additions and 37 deletions
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12
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -174,12 +174,12 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 ,true},
{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 ,true},
{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 ,true},
{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 ,true},
{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 ,true},
{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 ,true},
{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 ,true},
{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 ,true},
{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 ,false},
{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 ,false},
{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 ,false},
{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 ,false},
{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 ,false},
{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 ,false},
{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 ,true},
{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 ,true},

44
lib/Target/ARM/ARMInstrNEON.td
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@ -101,6 +101,14 @@ def VecListFourDAsmOperand : AsmOperandClass {
def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
let ParserMatchClass = VecListFourDAsmOperand;
}
// Register list of two D registers spaced by 2 (two sequential Q registers).
def VecListTwoQAsmOperand : AsmOperandClass {
let Name = "VecListTwoQ";
let ParserMethod = "parseVectorList";
}
def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
let ParserMatchClass = VecListTwoQAsmOperand;
}
//===----------------------------------------------------------------------===//
// NEON-specific DAG Nodes.
@ -395,10 +403,10 @@ def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
// VLD2 : Vector Load (multiple 2-element structures)
class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
: NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
(ins addrmode6:$Rn), IIC_VLD2,
"vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
"vld2", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
@ -413,9 +421,9 @@ class VLD2Q<bits<4> op7_4, string Dt>
let DecoderMethod = "DecodeVLDInstruction";
}
def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
@ -430,10 +438,10 @@ def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
// ...with address register writeback:
class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
: NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
"vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
"vld2", Dt, "$Vd, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
@ -448,9 +456,9 @@ class VLD2QWB<bits<4> op7_4, string Dt>
let DecoderMethod = "DecodeVLDInstruction";
}
def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
@ -465,12 +473,12 @@ def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
// ...with double-spaced registers
def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
// VLD3 : Vector Load (multiple 3-element structures)
class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>

14
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -930,6 +930,13 @@ public:
return VectorList.Count == 4;
}
bool isVecListTwoQ() const {
if (Kind != k_VectorList) return false;
//FIXME: We haven't taught the parser to handle by-two register lists
// yet, so don't pretend to know one.
return VectorList.Count == 2 && false;
}
bool isVectorIndex8() const {
if (Kind != k_VectorIndex) return false;
return VectorIndex.Val < 8;
@ -1543,6 +1550,13 @@ public:
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));

6
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1959,12 +1959,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second output register
switch (Inst.getOpcode()) {
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8_UPD:
case ARM::VLD2d16_UPD:
case ARM::VLD2d32_UPD:
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:

14
test/MC/ARM/neon-vld-encoding.s
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@ -35,17 +35,17 @@
@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4]
@ vld2.8 {d16, d17}, [r0, :64]
@ vld2.16 {d16, d17}, [r0, :128]
@ vld2.32 {d16, d17}, [r0]
vld2.8 {d16, d17}, [r0, :64]
vld2.16 {d16, d17}, [r0, :128]
vld2.32 {d16, d17}, [r0]
@ vld2.8 {d16, d17, d18, d19}, [r0, :64]
@ vld2.16 {d16, d17, d18, d19}, [r0, :128]
@ vld2.32 {d16, d17, d18, d19}, [r0, :256]
@ FIXME: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
@ FIXME: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
@ FIXME: vld2.32 {d16, d17}, [r0]@ encoding: [0x8f,0x08,0x60,0xf4]
@ FIXME: vld2.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x03,0x60,0xf4]
@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4]
@ FIXME: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4]
@ FIXME: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4]
@ FIXME: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4]

1
utils/TableGen/EDEmitter.cpp
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@ -575,6 +575,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
REG("VecListTwoD");
REG("VecListThreeD");
REG("VecListFourD");
REG("VecListTwoQ");
IMM("i32imm");
IMM("i32imm_hilo16");