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Scavenger asserts.
Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier. Allow redefinition of a sub-register of a live register. llvm-svn: 77904
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@ -113,6 +113,9 @@ public:
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bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
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bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
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/// isSuperRegUsed - Test if a super register is currently being used.
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bool isSuperRegUsed(unsigned Reg) const;
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/// getRegsUsed - return all registers currently in use in used.
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void getRegsUsed(BitVector &used, bool includeReserved);
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@ -57,6 +57,14 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI,
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return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
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}
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bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
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for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs)
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if (isUsed(SuperReg))
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return true;
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return false;
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}
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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@ -218,7 +226,7 @@ void RegScavenger::forward() {
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const MachineOperand MO = *UseMOs[i].first;
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unsigned Reg = MO.getReg();
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assert(isUsed(Reg) && "Using an undefined register!");
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assert((MO.isImplicit() || isUsed(Reg)) && "Using an undefined register!");
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if (MO.isKill() && !isReserved(Reg)) {
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KillRegs.set(Reg);
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@ -269,7 +277,8 @@ void RegScavenger::forward() {
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// Implicit def is allowed to "re-define" any register. Similarly,
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// implicitly defined registers can be clobbered.
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assert((isReserved(Reg) || isUnused(Reg) ||
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assert((MO.isImplicit() || isReserved(Reg) || isUnused(Reg) ||
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isSuperRegUsed(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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setUsed(Reg);
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@ -1,7 +1,4 @@
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; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs | FileCheck %s
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; XFAIL: *
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; Assertion failed: (isUsed(Reg) && "Using an undefined register!"),
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; function forward, file lib/CodeGen/RegisterScavenging.cpp, line 221.
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define i16 @f(i32* %p) nounwind {
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entry:
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