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ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary. llvm-svn: 146010
This commit is contained in:
Jim Grosbach
parent
d3e5443796
commit
a740cc6bc9
@ -1997,74 +1997,12 @@ class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
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// VFP/NEON Instruction aliases for type suffices.
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class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
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InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
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multiclass VFPDT8ReqInstAlias<string opc, string asm, dag Result> {
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def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
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def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
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def U8 : VFPDataTypeInstAlias<opc, ".u8", asm, Result>;
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def P8 : VFPDataTypeInstAlias<opc, ".p8", asm, Result>;
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}
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// VFPDT8ReqInstAlias plus plain ".8"
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multiclass VFPDT8InstAlias<string opc, string asm, dag Result> {
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def _8 : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
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defm _ : VFPDT8ReqInstAlias<opc, asm, Result>;
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}
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multiclass VFPDT16ReqInstAlias<string opc, string asm, dag Result> {
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def I16 : VFPDataTypeInstAlias<opc, ".i16", asm, Result>;
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def S16 : VFPDataTypeInstAlias<opc, ".s16", asm, Result>;
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def U16 : VFPDataTypeInstAlias<opc, ".u16", asm, Result>;
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def P16 : VFPDataTypeInstAlias<opc, ".p16", asm, Result>;
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}
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// VFPDT16ReqInstAlias plus plain ".16"
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multiclass VFPDT16InstAlias<string opc, string asm, dag Result> {
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def _16 : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
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defm _ : VFPDT16ReqInstAlias<opc, asm, Result>;
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}
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multiclass VFPDT32ReqInstAlias<string opc, string asm, dag Result> {
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def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
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def S32 : VFPDataTypeInstAlias<opc, ".s32", asm, Result>;
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def U32 : VFPDataTypeInstAlias<opc, ".u32", asm, Result>;
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def F32 : VFPDataTypeInstAlias<opc, ".f32", asm, Result>;
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def F : VFPDataTypeInstAlias<opc, ".f", asm, Result>;
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}
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// VFPDT32ReqInstAlias plus plain ".32"
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multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
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def _32 : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
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defm _ : VFPDT32ReqInstAlias<opc, asm, Result>;
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}
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multiclass VFPDT64ReqInstAlias<string opc, string asm, dag Result> {
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def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
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def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
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def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;
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def F64 : VFPDataTypeInstAlias<opc, ".f64", asm, Result>;
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def D : VFPDataTypeInstAlias<opc, ".d", asm, Result>;
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}
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// VFPDT64ReqInstAlias plus plain ".64"
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multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
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def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
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defm _ : VFPDT64ReqInstAlias<opc, asm, Result>;
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}
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multiclass VFPDT64NoF64ReqInstAlias<string opc, string asm, dag Result> {
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def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
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def S64 : VFPDataTypeInstAlias<opc, ".s64", asm, Result>;
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def U64 : VFPDataTypeInstAlias<opc, ".u64", asm, Result>;
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def D : VFPDataTypeInstAlias<opc, ".d", asm, Result>;
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}
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// VFPDT64ReqInstAlias plus plain ".64"
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multiclass VFPDT64NoF64InstAlias<string opc, string asm, dag Result> {
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def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
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defm _ : VFPDT64ReqInstAlias<opc, asm, Result>;
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}
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multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
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defm _ : VFPDT8InstAlias<opc, asm, Result>;
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defm _ : VFPDT16InstAlias<opc, asm, Result>;
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defm _ : VFPDT32InstAlias<opc, asm, Result>;
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defm _ : VFPDT64InstAlias<opc, asm, Result>;
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}
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multiclass VFPDTAnyNoF64InstAlias<string opc, string asm, dag Result> {
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defm _ : VFPDT8InstAlias<opc, asm, Result>;
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defm _ : VFPDT16InstAlias<opc, asm, Result>;
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defm _ : VFPDT32InstAlias<opc, asm, Result>;
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defm _ : VFPDT64NoF64InstAlias<opc, asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
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}
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// The same alias classes using AsmPseudo instead, for the more complex
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@ -2151,10 +2089,13 @@ def : TokenAlias<".s16", ".i16">;
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def : TokenAlias<".u16", ".i16">;
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def : TokenAlias<".s32", ".i32">;
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def : TokenAlias<".u32", ".i32">;
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def : TokenAlias<".s64", ".i64">;
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def : TokenAlias<".u64", ".i64">;
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def : TokenAlias<".i8", ".8">;
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def : TokenAlias<".i16", ".16">;
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def : TokenAlias<".i32", ".32">;
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def : TokenAlias<".i64", ".64">;
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def : TokenAlias<".p8", ".8">;
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def : TokenAlias<".p16", ".16">;
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@ -4559,10 +4559,6 @@ def : InstAlias<"vmov${p} $Vd, $Vm",
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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def : InstAlias<"vmov${p} $Vd, $Vm",
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(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
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defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm",
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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defm : VFPDTAnyNoF64InstAlias<"vmov${p}", "$Vd, $Vm",
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(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
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// VMOV : Vector Move (Immediate)
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@ -5315,329 +5311,6 @@ defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
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defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
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(VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
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// VLD1 requires a size suffix, but also accepts type specific variants.
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// Load one D register.
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d8 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d16 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d32 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d64 VecListOneD:$Vd, addrmode6:$Rn, pred:$p)>;
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// with writeback, fixed stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d8wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d16wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d32wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d64wb_fixed VecListOneD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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// with writeback, register stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d8wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d16wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d32wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d64wb_register VecListOneD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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// Load two D registers.
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1q8 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1q16 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1q32 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1q64 VecListTwoD:$Vd, addrmode6:$Rn, pred:$p)>;
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// with writeback, fixed stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1q8wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1q16wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1q32wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1q64wb_fixed VecListTwoD:$Vd, zero_reg, addrmode6:$Rn, pred:$p)>;
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// with writeback, register stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1q8wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1q16wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1q32wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1q64wb_register VecListTwoD:$Vd, zero_reg, addrmode6:$Rn,
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rGPR:$Rm, pred:$p)>;
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// Load three D registers.
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d8T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d16T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d32T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d64T VecListThreeD:$Vd, addrmode6:$Rn, pred:$p)>;
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// with writeback, fixed stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d8Twb_fixed VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d16Twb_fixed VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d32Twb_fixed VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d64Twb_fixed VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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// with writeback, register stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d8Twb_register VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d16Twb_register VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d32Twb_register VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d64Twb_register VecListThreeD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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// Load four D registers.
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d8Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d16Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d32Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn",
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(VLD1d64Q VecListFourD:$Vd, addrmode6:$Rn, pred:$p)>;
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// with writeback, fixed stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d8Qwb_fixed VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d16Qwb_fixed VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d32Qwb_fixed VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn!",
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(VLD1d64Qwb_fixed VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, pred:$p)>;
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// with writeback, register stride
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defm : VFPDT8ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d8Qwb_register VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d16Qwb_register VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d32Qwb_register VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vld1${p}", "$Vd, $Rn, $Rm",
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(VLD1d64Qwb_register VecListFourD:$Vd, zero_reg,
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addrmode6:$Rn, rGPR:$Rm, pred:$p)>;
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// VST1 requires a size suffix, but also accepts type specific variants.
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// Store one D register.
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defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
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(VST1d8 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
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(VST1d16 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
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(VST1d32 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
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(VST1d64 addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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// with writeback, fixed stride
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defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
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(VST1d8wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
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(VST1d16wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
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(VST1d32wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
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(VST1d64wb_fixed zero_reg, addrmode6:$Rn, VecListOneD:$Vd, pred:$p)>;
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// with writeback, register stride
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defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
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(VST1d8wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
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VecListOneD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d16wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListOneD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d32wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListOneD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d64wb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListOneD:$Vd, pred:$p)>;
|
||||
|
||||
// Store two D registers.
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1q8 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1q16 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1q32 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1q64 addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
// with writeback, fixed stride
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1q8wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1q16wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1q32wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1q64wb_fixed zero_reg, addrmode6:$Rn, VecListTwoD:$Vd, pred:$p)>;
|
||||
// with writeback, register stride
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1q8wb_register zero_reg, addrmode6:$Rn,
|
||||
rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1q16wb_register zero_reg, addrmode6:$Rn,
|
||||
rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1q32wb_register zero_reg, addrmode6:$Rn,
|
||||
rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1q64wb_register zero_reg, addrmode6:$Rn,
|
||||
rGPR:$Rm, VecListTwoD:$Vd, pred:$p)>;
|
||||
|
||||
// Load three D registers.
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d8T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d16T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d32T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d64T addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d8Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d16Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d32Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d64Twb_fixed zero_reg, addrmode6:$Rn, VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d8Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d16Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d32Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListThreeD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d64Twb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListThreeD:$Vd, pred:$p)>;
|
||||
|
||||
// Load four D registers.
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d8Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d16Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d32Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn",
|
||||
(VST1d64Q addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d8Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d16Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d32Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn!",
|
||||
(VST1d64Qwb_fixed zero_reg, addrmode6:$Rn, VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT8ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d8Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d16Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d32Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListFourD:$Vd, pred:$p)>;
|
||||
defm : VFPDT64ReqInstAlias<"vst1${p}", "$Vd, $Rn, $Rm",
|
||||
(VST1d64Qwb_register zero_reg, addrmode6:$Rn, rGPR:$Rm,
|
||||
VecListFourD:$Vd, pred:$p)>;
|
||||
|
||||
|
||||
// VTRN instructions data type suffix aliases for more-specific types.
|
||||
defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Dd, $Dm",
|
||||
(VTRNd8 DPR:$Dd, DPR:$Dm, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
|
||||
(VTRNd16 DPR:$Dd, DPR:$Dm, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Dd, $Dm",
|
||||
(VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
|
||||
|
||||
defm : VFPDT8ReqInstAlias <"vtrn${p}", "$Qd, $Qm",
|
||||
(VTRNq8 QPR:$Qd, QPR:$Qm, pred:$p)>;
|
||||
defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
|
||||
(VTRNq16 QPR:$Qd, QPR:$Qm, pred:$p)>;
|
||||
defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
|
||||
(VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;
|
||||
|
||||
// VEXT instructions data type suffix aliases for more-specific types.
|
||||
defm VEXTd : VFPDT8ReqInstAlias <"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTd8 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_7:$index, pred:$p)>;
|
||||
defm VEXTd : VFPDT16ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTd16 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_3:$index, pred:$p)>;
|
||||
defm VEXTd : VFPDT32ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTd32 DPR:$Vd, DPR:$Vn, DPR:$Vm, imm0_1:$index, pred:$p)>;
|
||||
|
||||
defm VEXTq : VFPDT8ReqInstAlias <"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTq8 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_15:$index, pred:$p)>;
|
||||
defm VEXTq : VFPDT16ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTq16 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_7:$index, pred:$p)>;
|
||||
defm VEXTq : VFPDT32ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTq32 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_3:$index, pred:$p)>;
|
||||
defm VEXTq : VFPDT64ReqInstAlias<"vext${p}", "$Vd, $Vn, $Vm, $index",
|
||||
(VEXTq64 QPR:$Vd, QPR:$Vn, QPR:$Vm, imm0_1:$index, pred:$p)>;
|
||||
|
||||
// VMUL instructions data type suffix aliases for more-specific types.
|
||||
def : NEONInstAlias<"vmul${p}.s16 $Dd, $Dn $Dm$lane",
|
||||
(VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s16 $Qd, $Qn, $Dm$lane",
|
||||
(VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u16 $Dd, $Dn $Dm$lane",
|
||||
(VMULslv4i16 DPR:$Dd, DPR:$Dn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u16 $Qd, $Qn, $Dm$lane",
|
||||
(VMULslv8i16 QPR:$Qd, QPR:$Qn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
|
||||
def : NEONInstAlias<"vmul${p}.s32 $Dd, $Dn $Dm$lane",
|
||||
(VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s32 $Qd, $Qn, $Dm$lane",
|
||||
(VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u32 $Dd, $Dn $Dm$lane",
|
||||
(VMULslv2i32 DPR:$Dd, DPR:$Dn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u32 $Qd, $Qn, $Dm$lane",
|
||||
(VMULslv4i32 QPR:$Qd, QPR:$Qn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
|
||||
// VMUL two-operand aliases.
|
||||
def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
|
||||
(VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
|
||||
@ -5645,18 +5318,6 @@ def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
|
||||
def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
|
||||
(VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s16 $Ddn, $Dm$lane",
|
||||
(VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s16 $Qdn, $Dm$lane",
|
||||
(VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u16 $Ddn, $Dm$lane",
|
||||
(VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u16 $Qdn, $Dm$lane",
|
||||
(VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
|
||||
VectorIndex16:$lane, pred:$p)>;
|
||||
|
||||
def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
|
||||
(VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
|
||||
@ -5664,18 +5325,6 @@ def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
|
||||
def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
|
||||
(VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s32 $Ddn, $Dm$lane",
|
||||
(VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.s32 $Qdn, $Dm$lane",
|
||||
(VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u32 $Ddn, $Dm$lane",
|
||||
(VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
def : NEONInstAlias<"vmul${p}.u32 $Qdn, $Dm$lane",
|
||||
(VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
|
||||
VectorIndex32:$lane, pred:$p)>;
|
||||
|
||||
def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
|
||||
(VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
|
||||
@ -5740,3 +5389,10 @@ defm VST1LNdWB_register_Asm :
|
||||
NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
|
||||
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
|
||||
rGPR:$Rm, pred:$p)>;
|
||||
|
||||
// VMOV takes an optional datatype suffix
|
||||
defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
|
||||
(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
|
||||
defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
|
||||
(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
|
||||
|
||||
|
||||
@ -1164,14 +1164,14 @@ def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
|
||||
def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
|
||||
|
||||
// VLDR/VSTR accept an optional type suffix.
|
||||
defm : VFPDT32InstAlias<"vldr${p}", "$Sd, $addr",
|
||||
(VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
|
||||
defm : VFPDT32InstAlias<"vstr${p}", "$Sd, $addr",
|
||||
(VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
|
||||
defm : VFPDT64InstAlias<"vldr${p}", "$Dd, $addr",
|
||||
(VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
|
||||
defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
|
||||
(VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
|
||||
def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
|
||||
(VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
|
||||
def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
|
||||
(VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
|
||||
def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
|
||||
(VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
|
||||
def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
|
||||
(VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
|
||||
|
||||
// VMUL has a two-operand form (implied destination operand)
|
||||
def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user