RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
Code Issues Projects Releases Wiki Activity

[ARM][Asm] Debug trace for the processInstruction loop

Browse Source 
In the Arm assembly parser, we first match an instruction, then call
processInstruction to possibly change it to a different encoding, to
match rules in the architecture manual which can't be expressed by the
table-generated matcher.

This adds debug printing so that this process is visible when using the
-debug option.

To support this, I've added a new overload of MCInst::dump_pretty which
takes the opcode name as a StringRef, since we don't have an InstPrinter
instance in the assembly parser. Instead, we can get the same
information directly from the MCInstrInfo.

Differential revision: https://reviews.llvm.org/D54852

llvm-svn: 348113
This commit is contained in:
Oliver Stannard 2018-12-03 10:21:28 +00:00
parent 8e6b80a242
commit a7553313be
3 changed files with 18 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/MC/MCInst.h
View File

@ -208,6 +208,8 @@ public:
/// string.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer = nullptr,
StringRef Separator = " ") const;
void dump_pretty(raw_ostream &OS, StringRef Name,
StringRef Separator = " ") const;
};
inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) {

12
lib/MC/MCInst.cpp
View File

@ -72,11 +72,17 @@ void MCInst::print(raw_ostream &OS) const {
void MCInst::dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer,
StringRef Separator) const {
StringRef InstName = Printer ? Printer->getOpcodeName(getOpcode()) : "";
dump_pretty(OS, InstName, Separator);
}
void MCInst::dump_pretty(raw_ostream &OS, StringRef Name,
StringRef Separator) const {
OS << "<MCInst #" << getOpcode();
// Show the instruction opcode name if we have access to a printer.
if (Printer)
OS << ' ' << Printer->getOpcodeName(getOpcode());
// Show the instruction opcode name if we have it.
if (!Name.empty())
OS << ' ' << Name;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
OS << Separator;

8
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -9310,6 +9310,10 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
switch (MatchResult) {
case Match_Success:
LLVM_DEBUG(dbgs() << "Parsed as: ";
Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
dbgs() << "\n");
// Context sensitive operand constraints aren't handled by the matcher,
// so check them here.
if (validateInstruction(Inst, Operands)) {
@ -9327,7 +9331,9 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// individual transformations can chain off each other. E.g.,
// tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
while (processInstruction(Inst, Operands, Out))
;
LLVM_DEBUG(dbgs() << "Changed to: ";
Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
dbgs() << "\n");
// Only after the instruction is fully processed, we can validate it
if (wasInITBlock && hasV8Ops() && isThumb() &&