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ScheduleDAGInstrs: Remove IsPostRA flag; NFC

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ScheduleDAGInstrs doesn't behave differently before or after register
allocation. It was only used in a method of MachineSchedulerBase which
behaved differently in MachineScheduler/PostMachineScheduler. Change
this to let MachineScheduler/PostMachineScheduler just pass in a
parameter to that function.

The order of the LiveIntervals* and bool RemoveKillFlags paramters have
been switched to make out-of-tree code fail instead of unintentionally
passing a value intended for the IsPostRA flag to the (previously
following and default initialized) RemoveKillFlags.

Differential Revision: http://reviews.llvm.org/D14245

llvm-svn: 251883
This commit is contained in:
Matthias Braun 2015-11-03 01:53:29 +00:00
parent 2faf05c4dc
commit a75cf73a70
9 changed files with 35 additions and 53 deletions
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2
include/llvm/CodeGen/DFAPacketizer.h
View File

@ -106,7 +106,7 @@ protected:
std::map<MachineInstr*, SUnit*> MIToSUnit;
public:
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA);
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI);
virtual ~VLIWPacketizerList();

7
include/llvm/CodeGen/MachineScheduler.h
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@ -254,9 +254,8 @@ protected:
#endif
public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool IsPostRA)
: ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA,
/*RemoveKillFlags=*/IsPostRA, C->LIS),
bool RemoveKillFlags)
: ScheduleDAGInstrs(*C->MF, C->MLI, C->LIS, RemoveKillFlags),
AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
#ifndef NDEBUG
@ -386,7 +385,7 @@ protected:
public:
ScheduleDAGMILive(MachineSchedContext *C,
std::unique_ptr<MachineSchedStrategy> S)
: ScheduleDAGMI(C, std::move(S), /*IsPostRA=*/false),
: ScheduleDAGMI(C, std::move(S), /*RemoveKillFlags=*/false),
RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
ShouldTrackPressure(false), RPTracker(RegPressure),
TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}

2
include/llvm/CodeGen/Passes.h
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@ -226,7 +226,7 @@ public:
///
/// This can also be used to plug a new MachineSchedStrategy into an instance
/// of the standard ScheduleDAGMI:
/// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
/// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
///
/// Return NULL to select the default (generic) machine scheduler.
virtual ScheduleDAGInstrs *

10
include/llvm/CodeGen/ScheduleDAGInstrs.h
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@ -84,9 +84,6 @@ namespace llvm {
/// TargetSchedModel provides an interface to the machine model.
TargetSchedModel SchedModel;
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
/// True if the DAG builder should remove kill flags (in preparation for
/// rescheduling).
bool RemoveKillFlags;
@ -154,14 +151,11 @@ namespace llvm {
public:
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo *mli,
bool IsPostRAFlag,
bool RemoveKillFlags = false,
LiveIntervals *LIS = nullptr);
LiveIntervals *LIS = nullptr,
bool RemoveKillFlags = false);
~ScheduleDAGInstrs() override {}
bool isPostRA() const { return IsPostRA; }
/// \brief Expose LiveIntervals for use in DAG mutators and such.
LiveIntervals *getLIS() const { return LIS; }

11
lib/CodeGen/DFAPacketizer.cpp
View File

@ -105,16 +105,15 @@ namespace llvm {
// Schedule method to build the dependence graph.
class DefaultVLIWScheduler : public ScheduleDAGInstrs {
public:
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
bool IsPostRA);
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI);
// Schedule - Actual scheduling work.
void schedule() override;
};
}
DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
MachineLoopInfo &MLI, bool IsPostRA)
: ScheduleDAGInstrs(MF, &MLI, IsPostRA) {
MachineLoopInfo &MLI)
: ScheduleDAGInstrs(MF, &MLI) {
CanHandleTerminators = true;
}
@ -125,11 +124,11 @@ void DefaultVLIWScheduler::schedule() {
// VLIWPacketizerList Ctor
VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
MachineLoopInfo &MLI, bool IsPostRA)
MachineLoopInfo &MLI)
: MF(MF) {
TII = MF.getSubtarget().getInstrInfo();
ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA);
VLIWScheduler = new DefaultVLIWScheduler(MF, MLI);
}
// VLIWPacketizerList Dtor

30
lib/CodeGen/MachineScheduler.cpp
View File

@ -111,7 +111,7 @@ public:
void print(raw_ostream &O, const Module* = nullptr) const override;
protected:
void scheduleRegions(ScheduleDAGInstrs &Scheduler);
void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
/// MachineScheduler runs after coalescing and before register allocation.
@ -340,7 +340,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
// Instantiate the selected scheduler for this target, function, and
// optimization level.
std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
scheduleRegions(*Scheduler);
scheduleRegions(*Scheduler, false);
DEBUG(LIS->dump());
if (VerifyScheduling)
@ -368,7 +368,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
// Instantiate the selected scheduler for this target, function, and
// optimization level.
std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
scheduleRegions(*Scheduler);
scheduleRegions(*Scheduler, true);
if (VerifyScheduling)
MF->verify(this, "After post machine scheduling.");
@ -388,15 +388,14 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
static bool isSchedBoundary(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB,
MachineFunction *MF,
const TargetInstrInfo *TII,
bool IsPostRA) {
const TargetInstrInfo *TII) {
return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
}
/// Main driver for both MachineScheduler and PostMachineScheduler.
void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
bool FixKillFlags) {
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
bool IsPostRA = Scheduler.isPostRA();
// Visit all machine basic blocks.
//
@ -434,7 +433,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
// Avoid decrementing RegionEnd for blocks with no terminator.
if (RegionEnd != MBB->end() ||
isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII, IsPostRA)) {
isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII)) {
--RegionEnd;
// Count the boundary instruction.
--RemainingInstrs;
@ -445,7 +444,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
unsigned NumRegionInstrs = 0;
MachineBasicBlock::iterator I = RegionEnd;
for(;I != MBB->begin(); --I, --RemainingInstrs) {
if (isSchedBoundary(&*std::prev(I), &*MBB, MF, TII, IsPostRA))
if (isSchedBoundary(&*std::prev(I), &*MBB, MF, TII))
break;
if (!I->isDebugValue())
++NumRegionInstrs;
@ -461,8 +460,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
Scheduler.exitRegion();
continue;
}
DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "")
<< "MI Scheduling **********\n");
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(dbgs() << MF->getName()
<< ":BB#" << MBB->getNumber() << " " << MBB->getName()
<< "\n From: " << *I << " To: ";
@ -489,11 +487,11 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
}
assert(RemainingInstrs == 0 && "Instruction count mismatch!");
Scheduler.finishBlock();
if (Scheduler.isPostRA()) {
// FIXME: Ideally, no further passes should rely on kill flags. However,
// thumb2 size reduction is currently an exception.
Scheduler.fixupKills(&*MBB);
}
// FIXME: Ideally, no further passes should rely on kill flags. However,
// thumb2 size reduction is currently an exception, so the PostMIScheduler
// needs to do this.
if (FixKillFlags)
Scheduler.fixupKills(&*MBB);
}
Scheduler.finalizeSchedule();
}

2
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -196,7 +196,7 @@ SchedulePostRATDList::SchedulePostRATDList(
const RegisterClassInfo &RCI,
TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
: ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
: ScheduleDAGInstrs(MF, &MLI), AA(AA), EndIndex(0) {
const InstrItineraryData *InstrItins =
MF.getSubtarget().getInstrItineraryData();

21
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -51,15 +51,12 @@ static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo *mli,
bool IsPostRAFlag, bool RemoveKillFlags,
LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
CanHandleTerminators(false), FirstDbgValue(nullptr) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
LiveIntervals *LIS,
bool RemoveKillFlags)
: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(LIS),
RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
FirstDbgValue(nullptr) {
DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
"Virtual registers must be removed prior to PostRA scheduling");
const TargetSubtargetInfo &ST = mf.getSubtarget();
SchedModel.init(ST.getSchedModel(), &ST, TII);
@ -230,11 +227,8 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
if (TRI->isPhysicalRegister(Reg))
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
else {
assert(!IsPostRA && "Virtual register encountered after regalloc.");
if (MO.readsReg()) // ignore undef operands
addVRegUseDeps(&ExitSU, i);
}
else if (MO.readsReg()) // ignore undef operands
addVRegUseDeps(&ExitSU, i);
}
} else {
// For others, e.g. fallthrough, conditional branch, assume the exit
@ -831,7 +825,6 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
if (TRI->isPhysicalRegister(Reg))
addPhysRegDeps(SU, j);
else {
assert(!IsPostRA && "Virtual register encountered!");
if (MO.isDef()) {
HasVRegDef = true;
addVRegDefDeps(SU, j);

3
lib/Target/AMDGPU/R600Packetizer.cpp
View File

@ -149,8 +149,7 @@ private:
public:
// Ctor.
R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI)
: VLIWPacketizerList(MF, MLI, true),
TII(static_cast<const R600InstrInfo *>(
: VLIWPacketizerList(MF, MLI), TII(static_cast<const R600InstrInfo *>(
MF.getSubtarget().getInstrInfo())),
TRI(TII->getRegisterInfo()) {
VLIW5 = !MF.getSubtarget<AMDGPUSubtarget>().hasCaymanISA();