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[AArch64] Avoid pairing loads with same result reg
When pairing ldr instructions to an ldp instruction, we cannot pair two ldr destination registers where one is a sub or super register of the other. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D86906
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@ -1550,10 +1550,12 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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continue;
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}
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}
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// If the destination register of the loads is the same register, bail
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// and keep looking. A load-pair instruction with both destination
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// registers the same is UNPREDICTABLE and will result in an exception.
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if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
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// If the destination register of one load is the same register or a
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// sub/super register of the other load, bail and keep looking. A
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// load-pair instruction with both destination registers the same is
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// UNPREDICTABLE and will result in an exception.
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if (MayLoad &&
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TRI->isSuperOrSubRegisterEq(Reg, getLdStRegOp(MI).getReg())) {
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LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits,
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TRI);
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MemInsns.push_back(&MI);
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39
test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir
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39
test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir
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@ -0,0 +1,39 @@
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# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
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#
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# The test below tests that when the AArch64 Load Store Optimization pass tries to
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# convert load instructions into a ldp instruction, and when the destination
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# registers are sub/super register of each other, then the convertion should not occur.
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#
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# For example, for the following pattern:
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# ldr x10 [x9]
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# ldr w10 [x9, 8],
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# We cannot convert it to an ldp instruction.
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#
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# CHECK-NOT: LDP
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# CHECK: $x10 = LDRSWui $x9, 0
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# CHECK: $w10 = LDRWui $x9, 1
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# CHECK: RET
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---
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name: test1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x9
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$x10 = LDRSWui $x9, 0 :: (load 4)
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$w10 = LDRWui $x9, 1 :: (load 4)
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RET undef $lr, implicit undef $w0
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...
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# CHECK-NOT: LDP
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# CHECK: $w10 = LDRWui $x9, 0
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# CHECK: $x10 = LDRSWui $x9, 1
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# CHECK: RET
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---
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name: test2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x9
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$w10 = LDRWui $x9, 0 :: (load 4)
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$x10 = LDRSWui $x9, 1 :: (load 4)
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RET undef $lr, implicit undef $w0
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...
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