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ARM: Initialize LoadStore passes in TargetMachine

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Initializing them in LLVMInitializeARMTarget() makes them visible early
enough for "llc -run-pass usage".

This required the pass to be renamed from "arm-load-store-opt" to
"arm-ldst-opt", because there already exists an arm-load-store-opt
cl::opt switch which would now clash with the passname getting added as
a switch in opt. On the bright side the pass name now matches the
DEBUG_TYPE name. Renamed "arm-prera-load-store-opt" to
"arm-repra-ldst-opt" as well for consistency.

llvm-svn: 275661
This commit is contained in:
Matthias Braun 2016-07-16 02:24:10 +00:00
parent 42bc7dba74
commit a7831bc33a
3 changed files with 13 additions and 16 deletions
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4
lib/Target/ARM/ARM.h
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@ -27,6 +27,7 @@ class FunctionPass;
class ImmutablePass; class ImmutablePass;
class MachineInstr; class MachineInstr;
class MCInst; class MCInst;
class PassRegistry;
class TargetLowering; class TargetLowering;
class TargetMachine; class TargetMachine;
@ -45,6 +46,9 @@ FunctionPass *createThumb2SizeReductionPass(
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
ARMAsmPrinter &AP); ARMAsmPrinter &AP);
void initializeARMLoadStoreOptPass(PassRegistry &);
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
} // end namespace llvm; } // end namespace llvm;
#endif #endif

21
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -69,10 +69,6 @@ static cl::opt<bool>
AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden, AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
cl::init(false), cl::desc("Be more conservative in ARM load/store opt")); cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
namespace llvm {
void initializeARMLoadStoreOptPass(PassRegistry &);
}
#define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass" #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
namespace { namespace {
@ -80,9 +76,7 @@ namespace {
/// form ldm / stm instructions. /// form ldm / stm instructions.
struct ARMLoadStoreOpt : public MachineFunctionPass { struct ARMLoadStoreOpt : public MachineFunctionPass {
static char ID; static char ID;
ARMLoadStoreOpt() : MachineFunctionPass(ID) { ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
initializeARMLoadStoreOptPass(*PassRegistry::getPassRegistry());
}
const MachineFunction *MF; const MachineFunction *MF;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
@ -172,7 +166,8 @@ namespace {
char ARMLoadStoreOpt::ID = 0; char ARMLoadStoreOpt::ID = 0;
} }
INITIALIZE_PASS(ARMLoadStoreOpt, "arm-load-store-opt", ARM_LOAD_STORE_OPT_NAME, false, false) INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
false)
static bool definesCPSR(const MachineInstr &MI) { static bool definesCPSR(const MachineInstr &MI) {
for (const auto &MO : MI.operands()) { for (const auto &MO : MI.operands()) {
@ -1939,10 +1934,6 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
return Modified; return Modified;
} }
namespace llvm {
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
}
#define ARM_PREALLOC_LOAD_STORE_OPT_NAME \ #define ARM_PREALLOC_LOAD_STORE_OPT_NAME \
"ARM pre- register allocation load / store optimization pass" "ARM pre- register allocation load / store optimization pass"
@ -1951,9 +1942,7 @@ namespace {
/// locations close to make it more likely they will be combined later. /// locations close to make it more likely they will be combined later.
struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{ struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
static char ID; static char ID;
ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) { ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
initializeARMPreAllocLoadStoreOptPass(*PassRegistry::getPassRegistry());
}
const DataLayout *TD; const DataLayout *TD;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
@ -1984,7 +1973,7 @@ namespace {
char ARMPreAllocLoadStoreOpt::ID = 0; char ARMPreAllocLoadStoreOpt::ID = 0;
} }
INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-load-store-opt", INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {

4
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -54,6 +54,10 @@ extern "C" void LLVMInitializeARMTarget() {
RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget); RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget); RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget); RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
PassRegistry &Registry = *PassRegistry::getPassRegistry();
initializeARMLoadStoreOptPass(Registry);
initializeARMPreAllocLoadStoreOptPass(Registry);
} }
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {