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[SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.

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Summary:
This is used on AMDGPU for rounding from v3f64 (which is illegal) to
v3f32 (which is legal).

Subscribers: jvesely, nhaehnle, tpr, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69339
This commit is contained in:
Jay Foad 2019-10-23 14:22:16 +01:00
parent de7d2c4397
commit a785d0624f
2 changed files with 24 additions and 4 deletions
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18
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -4161,6 +4161,8 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::FP_EXTEND:
case ISD::STRICT_FP_EXTEND:
case ISD::FP_ROUND:
case ISD::STRICT_FP_ROUND:
case ISD::FP_TO_SINT:
case ISD::STRICT_FP_TO_SINT:
case ISD::FP_TO_UINT:
@ -4297,13 +4299,21 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
if (TLI.isTypeLegal(WideVT) && !N->isStrictFPOpcode()) {
SDValue Res;
if (N->isStrictFPOpcode()) {
Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
{ N->getOperand(0), InOp });
if (Opcode == ISD::STRICT_FP_ROUND)
Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
{ N->getOperand(0), InOp, N->getOperand(2) });
else
Res = DAG.getNode(Opcode, dl, { WideVT, MVT::Other },
{ N->getOperand(0), InOp });
// Legalize the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
} else
Res = DAG.getNode(Opcode, dl, WideVT, InOp);
} else {
if (Opcode == ISD::FP_ROUND)
Res = DAG.getNode(Opcode, dl, WideVT, InOp, N->getOperand(1));
else
Res = DAG.getNode(Opcode, dl, WideVT, InOp);
}
return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));

10
test/CodeGen/AMDGPU/fptrunc.ll
View File

@ -30,6 +30,16 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}fptrunc_v3f64_to_v3f32:
; GCN: v_cvt_f32_f64_e32
; GCN: v_cvt_f32_f64_e32
; GCN: v_cvt_f32_f64_e32
define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(<3 x float> addrspace(1)* %out, <3 x double> %in) {
%result = fptrunc <3 x double> %in to <3 x float>
store <3 x float> %result, <3 x float> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
; GCN: v_cvt_f32_f64_e32
; GCN: v_cvt_f32_f64_e32