From a78953e3c54bed13d5de7308f7ff919e39a23020 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 31 Mar 2016 19:42:04 +0000 Subject: [PATCH] [ARM] Expand v1i64 and v2i64 ctpop. The default is legal, which results in 'Cannot select' errors. This is triggered during selfhost due to a recent cost model change. llvm-svn: 265040 --- lib/Target/ARM/ARMISelLowering.cpp | 2 ++ test/CodeGen/ARM/popcnt.ll | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 8bdb32acbef..ecf15d3bd6f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -577,6 +577,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::CTPOP, MVT::v4i32, Custom); setOperationAction(ISD::CTPOP, MVT::v4i16, Custom); setOperationAction(ISD::CTPOP, MVT::v8i16, Custom); + setOperationAction(ISD::CTPOP, MVT::v1i64, Expand); + setOperationAction(ISD::CTPOP, MVT::v2i64, Expand); // NEON does not have single instruction CTTZ for vectors. setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll index 74f90640ca6..fd61811f49c 100644 --- a/test/CodeGen/ARM/popcnt.ll +++ b/test/CodeGen/ARM/popcnt.ll @@ -71,12 +71,28 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } +define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind { +; CHECK-LABEL: vcnt64: + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1) + ret <1 x i64> %tmp2 +} + +define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind { +; CHECK-LABEL: vcntQ64: + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1) + ret <2 x i64> %tmp2 +} + declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone +declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclz8: