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[VE] Support copy of vector mask registers

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Support VM and VMP registers in copyPhysReg() function.  Also add
regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D93547
This commit is contained in:
Kazushi (Jam) Marukawa 2020-12-19 01:01:24 +09:00
parent 87ab7fb0ff
commit a7e64248cb
2 changed files with 32 additions and 0 deletions
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15
lib/Target/VE/VEInstrInfo.cpp
View File

@ -341,6 +341,11 @@ static void copyPhysSubRegs(MachineBasicBlock &MBB,
MachineInstrBuilder MIB =
BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
MovMI = MIB.getInstr();
} else if (MCID.getOpcode() == VE::ANDMmm) {
// generate "ANDM, dest, vm0, src" instruction.
MachineInstrBuilder MIB =
BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc);
MovMI = MIB.getInstr();
} else {
llvm_unreachable("Unexpected reg-to-reg copy instruction");
}
@ -379,6 +384,16 @@ void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SubTmp, getKillRegState(true));
MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true);
} else if (VE::VMRegClass.contains(DestReg, SrcReg)) {
BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg)
.addReg(VE::VM0)
.addReg(SrcReg, getKillRegState(KillSrc));
} else if (VE::VM512RegClass.contains(DestReg, SrcReg)) {
// Use two instructions.
const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd};
unsigned int NumSubRegs = 2;
copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm),
NumSubRegs, SubRegIdx, &getRegisterInfo());
} else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
// Use two instructions.
const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};

17
test/CodeGen/VE/Vector/fastcc_callee.ll
View File

@ -120,3 +120,20 @@ define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32> %p0, <256 x i32> %p1,
; define <256 x i32> @vreg_arg_v256i32_r8(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6, <256 x i32> %p7, <256 x i32> %p8) {
; ret <256 x i32> %p8
; }
define fastcc <256 x i1> @vreg_arg_v256i1_vm7(<256 x i1> %vm1, <256 x i1> %vm2, <256 x i1> %vm3, <256 x i1> %vm4, <256 x i1> %vm5, <256 x i1> %vm6, <256 x i1> %vm7, <256 x i1> %vm8) {
; CHECK-LABEL: vreg_arg_v256i1_vm7:
; CHECK: # %bb.0:
; CHECK-NEXT: andm %vm1, %vm0, %vm6
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i1> %vm6
}
define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1> %vmp1, <512 x i1> %vmp2, <512 x i1> %vmp3, <512 x i1> %vmp4) {
; CHECK-LABEL: vreg_arg_v512i1_vmp3:
; CHECK: # %bb.0:
; CHECK-NEXT: andm %vm2, %vm0, %vm6
; CHECK-NEXT: andm %vm3, %vm0, %vm7
; CHECK-NEXT: b.l.t (, %s10)
ret <512 x i1> %vmp3
}