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[x86] fix pr29061

Browse Source 
https://bugs.llvm.org//show_bug.cgi?id=29061
Don't try referencing REX-needed regs when not on 64bit mode
Aligns to GCC

Differetial Revision: https://reviews.llvm.org/D37801

llvm-svn: 314203
This commit is contained in:
Coby Tayree 2017-09-26 13:28:05 +00:00
parent 3f431534a8
commit a898c4daa9
2 changed files with 52 additions and 6 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
View File

@ -36953,12 +36953,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Size == 1) Size = 8;
unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
if (DestReg > 0) {
Res.first = DestReg;
Res.second = Size == 8 ? &X86::GR8RegClass
: Size == 16 ? &X86::GR16RegClass
: Size == 32 ? &X86::GR32RegClass
: &X86::GR64RegClass;
assert(Res.second->contains(Res.first) && "Register in register class");
bool is64Bit = Subtarget.is64Bit();
const TargetRegisterClass *RC =
Size == 8 ? (is64Bit ? &X86::GR8RegClass : &X86::GR8_NOREXRegClass)
: Size == 16 ? (is64Bit ? &X86::GR16RegClass : &X86::GR16_NOREXRegClass)
: Size == 32 ? (is64Bit ? &X86::GR32RegClass : &X86::GR32_NOREXRegClass)
: &X86::GR64RegClass;
if (RC->contains(DestReg))
Res = std::make_pair(DestReg, RC);
} else {
// No register found/type mismatch.
Res.first = 0;

44
test/CodeGen/X86/pr29061.ll Normal file
View File

@ -0,0 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple i386-unknown-linux-gnu < %s | FileCheck %s
; Previously, a reference to SIL/DIL was being emitted
; but those aren't available unless on a 64bit mode
define void @t1(i8 signext %c) {
; CHECK-LABEL: t1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: # kill: %DI<def> %DI<kill> %EDI<kill>
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "", "{di},~{dirflag},~{fpsr},~{flags}"(i8 %c)
ret void
}
define void @t2(i8 signext %c) {
; CHECK-LABEL: t2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: # kill: %SI<def> %SI<kill> %ESI<kill>
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry:
tail call void asm sideeffect "", "{si},~{dirflag},~{fpsr},~{flags}"(i8 %c)
ret void
}