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Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating

the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.

llvm-svn: 121408
This commit is contained in:
Owen Anderson 2010-12-09 20:27:52 +00:00
parent 61fe7b9ee5
commit a8ac35b468
4 changed files with 17 additions and 6 deletions

View File

@ -25,7 +25,10 @@ struct MCFixupKindInfo {
enum FixupKindFlags {
/// Is this fixup kind PCrelative? This is used by the assembler backend to
/// evaluate fixup values in a target independent manner when possible.
FKF_IsPCRel = (1 << 0)
FKF_IsPCRel = (1 << 0),
// Should this fixup kind force a 4-byte aligned effective PC value?
FKF_IsAligned = (1 << 1)
};
/// A target specific name for the fixup kind. The names will be unique for

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@ -253,8 +253,15 @@ bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer,
if (IsResolved)
IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
if (IsPCRel)
Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
if (IsPCRel) {
bool ShouldAlignPC = Emitter.getFixupKindInfo(
Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
// PC should be aligned to a 4-byte value.
if (ShouldAlignPC)
Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
else
Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
}
return IsResolved;
}

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@ -100,10 +100,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
}
case ARM::fixup_arm_ldst_pcrel_12:
// ARM PC-relative values are offset by 8.
Value -= 6;
Value -= 4;
case ARM::fixup_t2_ldst_pcrel_12: {
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value -= 2;
Value -= 4;
bool isAdd = true;
if ((int64_t)Value < 0) {
Value = -Value;

View File

@ -47,7 +47,8 @@ public:
const static MCFixupKindInfo Infos[] = {
// name off bits flags
{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },