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Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic adjusted accordingly. llvm-svn: 121408
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@ -25,7 +25,10 @@ struct MCFixupKindInfo {
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enum FixupKindFlags {
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/// Is this fixup kind PCrelative? This is used by the assembler backend to
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/// evaluate fixup values in a target independent manner when possible.
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FKF_IsPCRel = (1 << 0)
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FKF_IsPCRel = (1 << 0),
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// Should this fixup kind force a 4-byte aligned effective PC value?
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FKF_IsAligned = (1 << 1)
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};
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/// A target specific name for the fixup kind. The names will be unique for
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@ -253,8 +253,15 @@ bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer,
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if (IsResolved)
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IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
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if (IsPCRel)
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Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
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if (IsPCRel) {
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bool ShouldAlignPC = Emitter.getFixupKindInfo(
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Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
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// PC should be aligned to a 4-byte value.
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if (ShouldAlignPC)
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Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
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else
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Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
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}
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return IsResolved;
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}
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@ -100,10 +100,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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}
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case ARM::fixup_arm_ldst_pcrel_12:
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// ARM PC-relative values are offset by 8.
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Value -= 6;
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Value -= 4;
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case ARM::fixup_t2_ldst_pcrel_12: {
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// Offset by 4, adjusted by two due to the half-word ordering of thumb.
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Value -= 2;
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Value -= 4;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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@ -47,7 +47,8 @@ public:
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const static MCFixupKindInfo Infos[] = {
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// name off bits flags
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{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAligned},
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{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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