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Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted the same between the two, though. See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format. llvm-svn: 99590
This commit is contained in:
Johnny Chen
parent
289846d250
commit
a8b02d6451
@ -64,6 +64,8 @@ def N1RegModImmFrm : Format<32>;
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def N2RegFrm : Format<33>;
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def NVCVTFrm : Format<34>;
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def NVDupLnFrm : Format<35>;
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def N2RegVShLFrm : Format<36>;
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def N2RegVShRFrm : Format<37>;
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// Misc flags.
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@ -1302,17 +1302,17 @@ class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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// Shift by immediate,
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// both double- and quad-register.
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class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, 0, op4,
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(outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm, itin,
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(outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), f, itin,
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OpcodeStr, Dt, "$dst, $src, $SIMM", "",
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[(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
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class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType Ty, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, 1, op4,
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(outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
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(outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), f, itin,
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OpcodeStr, Dt, "$dst, $src, $SIMM", "",
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[(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
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@ -1321,7 +1321,7 @@ class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, op6, op4,
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(outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegFrm,
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(outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), N2RegVShLFrm,
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IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
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[(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
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(i32 imm:$SIMM))))]>;
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@ -1331,7 +1331,7 @@ class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDNode OpNode>
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: N2VImm<op24, op23, op11_8, op7, op6, op4,
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(outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegFrm, itin,
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(outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), N2RegVShRFrm, itin,
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OpcodeStr, Dt, "$dst, $src, $SIMM", "",
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[(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
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(i32 imm:$SIMM))))]>;
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@ -1341,14 +1341,14 @@ class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
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: N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
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(ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
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(ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
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OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
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[(set DPR:$dst, (Ty (add DPR:$src1,
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(Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
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class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
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: N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
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(ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VPALiD,
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(ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
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OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
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[(set QPR:$dst, (Ty (add QPR:$src1,
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(Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
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@ -1356,15 +1356,15 @@ class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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// Shift by immediate and insert,
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// both double- and quad-register.
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class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
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Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
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: N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
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(ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiD,
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(ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
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OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
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[(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
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class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
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Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
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: N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
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(ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegFrm, IIC_VSHLiQ,
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(ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
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OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
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[(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
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@ -1824,46 +1824,46 @@ multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
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// Neon 2-register vector shift by immediate,
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// with f of either N2RegVShLFrm or N2RegVShRFrm
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// element sizes of 8, 16, 32 and 64 bits:
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multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode> {
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InstrItinClass itin, string OpcodeStr, string Dt,
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SDNode OpNode, Format f> {
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// 64-bit vector types.
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
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def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, itin,
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def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, itin,
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def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
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// imm6 = xxxxxx
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// 128-bit vector types.
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def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
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def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
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def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, itin,
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def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, itin,
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
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OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
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// imm6 = xxxxxx
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}
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// Neon Shift-Accumulate vector operations,
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// element sizes of 8, 16, 32 and 64 bits:
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multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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@ -1905,41 +1905,43 @@ multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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// Neon Shift-Insert vector operations,
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// with f of either N2RegVShLFrm or N2RegVShRFrm
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// element sizes of 8, 16, 32 and 64 bits:
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multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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string OpcodeStr, SDNode ShOp> {
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string OpcodeStr, SDNode ShOp,
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Format f> {
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// 64-bit vector types.
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def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "8", v8i8, ShOp> {
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f, OpcodeStr, "8", v8i8, ShOp> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "16", v4i16, ShOp> {
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f, OpcodeStr, "16", v4i16, ShOp> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "32", v2i32, ShOp> {
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f, OpcodeStr, "32", v2i32, ShOp> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
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OpcodeStr, "64", v1i64, ShOp>;
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f, OpcodeStr, "64", v1i64, ShOp>;
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// imm6 = xxxxxx
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// 128-bit vector types.
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def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "8", v16i8, ShOp> {
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f, OpcodeStr, "8", v16i8, ShOp> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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}
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def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "16", v8i16, ShOp> {
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f, OpcodeStr, "16", v8i16, ShOp> {
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let Inst{21-20} = 0b01; // imm6 = 01xxxx
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}
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def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
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OpcodeStr, "32", v4i32, ShOp> {
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f, OpcodeStr, "32", v4i32, ShOp> {
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let Inst{21} = 0b1; // imm6 = 1xxxxx
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}
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def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
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OpcodeStr, "64", v2i64, ShOp>;
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f, OpcodeStr, "64", v2i64, ShOp>;
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// imm6 = xxxxxx
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}
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@ -2578,10 +2580,13 @@ defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
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defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ,
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IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu, 0>;
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// VSHL : Vector Shift Left (Immediate)
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defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
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defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
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N2RegVShLFrm>;
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// VSHR : Vector Shift Right (Immediate)
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defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs>;
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defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru>;
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defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
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N2RegVShRFrm>;
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defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
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N2RegVShRFrm>;
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// VSHLL : Vector Shift Left Long
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defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
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@ -2612,8 +2617,10 @@ defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
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defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
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IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu,0>;
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// VRSHR : Vector Rounding Shift Right
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defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs>;
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defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru>;
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defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
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N2RegVShRFrm>;
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defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
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N2RegVShRFrm>;
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// VRSHRN : Vector Rounding Shift Right and Narrow
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defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
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@ -2625,10 +2632,13 @@ defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
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defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q,
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IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu,0>;
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// VQSHL : Vector Saturating Shift Left (Immediate)
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defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s", NEONvqshls>;
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defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u", NEONvqshlu>;
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defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
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N2RegVShLFrm>;
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defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
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N2RegVShLFrm>;
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// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
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defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D, "vqshlu","s",NEONvqshlsu>;
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defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
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N2RegVShLFrm>;
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// VQSHRN : Vector Saturating Shift Right and Narrow
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defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
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@ -2666,9 +2676,9 @@ defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
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defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
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// VSLI : Vector Shift Left and Insert
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defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli>;
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defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
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// VSRI : Vector Shift Right and Insert
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defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri>;
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defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
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// Vector Absolute and Saturating Absolute.
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