From a8d6339086026a9c073908b89002b32a255ca934 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 5 May 2020 11:27:12 +0100 Subject: [PATCH] [ARM] Correct the type on a predicate cast A PREDICATE_CAST(PREDICATE_CAST(X)) can be converted to a PREDICATE_CAST(X) as the operation can convert between any forms of predicates (v4i1/v8i1/v16i1/i32). Unfortunately I got the type wrong on one of the rarer converts, which would lead to invalid nodes during isel. This fixes it up to use the correct type. Differential Revision: https://reviews.llvm.org/D79402 --- lib/Target/ARM/ARMISelLowering.cpp | 3 +-- test/CodeGen/Thumb2/mve-pred-convert.ll | 26 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/Thumb2/mve-pred-convert.ll diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 68420fdf54b..fa4e83b5f66 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -13226,8 +13226,7 @@ PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { // If the valuetypes are the same, we can remove the cast entirely. if (Op->getOperand(0).getValueType() == VT) return Op->getOperand(0); - return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, - Op->getOperand(0).getValueType(), Op->getOperand(0)); + return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0)); } return SDValue(); diff --git a/test/CodeGen/Thumb2/mve-pred-convert.ll b/test/CodeGen/Thumb2/mve-pred-convert.ll new file mode 100644 index 00000000000..c24f6e46425 --- /dev/null +++ b/test/CodeGen/Thumb2/mve-pred-convert.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s + +define void @g(i8* %v) { +; CHECK-LABEL: g: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: movs r0, #63 +; CHECK-NEXT: vmov.i32 q0, #0x0 +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrbt.8 q0, [r0] +; CHECK-NEXT: bx lr +entry: + %0 = load i8, i8* %v, align 1 + %conv = zext i8 %0 to i32 + %broadcast.splatinsert = insertelement <16 x i32> undef, i32 %conv, i32 0 + %broadcast.splat = shufflevector <16 x i32> %broadcast.splatinsert, <16 x i32> undef, <16 x i32> zeroinitializer + %1 = and <16 x i32> %broadcast.splat, + %2 = icmp eq <16 x i32> %1, zeroinitializer + %3 = select <16 x i1> %2, <16 x i8> zeroinitializer, <16 x i8> + call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %3, <16 x i8>* undef, i32 1, <16 x i1> ) + ret void +} + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>) #1