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[ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ GPR.
In Thumb 1, with the new ADDCARRY / SUBCARRY the scheduler may need to do copies CPSR ↔ GPR but not all Thumb1 targets implement them. The schedule can attempt, before attempting a copy, to clone the instructions but it does not currently do that for nodes with input glue. In this patch we introduce a target-hook to let the hook decide if a glued machinenode is still eligible for copying. In this case these are ARM::tADCS and ARM::tSBCS . As a follow-up of this change we should actually implement the copies for the Thumb1 targets that do implement them and restrict the hook to the targets that can't really do such copy as these clones are not ideal. This change fixes PR35836. Differential Revision: https://reviews.llvm.org/D42051 llvm-svn: 323857
This commit is contained in:
Roger Ferrer Ibanez
parent
4c0185c682
commit
a8d946115e
@ -953,6 +953,10 @@ public:
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/// Return true when a target supports MachineCombiner.
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virtual bool useMachineCombiner() const { return false; }
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/// Return true if the given SDNode can be copied during scheduling
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/// even if it has glue.
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virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
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protected:
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/// Target-dependent implementation for foldMemoryOperand.
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/// Target-independent code in foldMemoryOperand will
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@ -1117,22 +1117,34 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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if (!N)
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return nullptr;
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if (SU->getNode()->getGluedNode())
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DEBUG(dbgs() << "Considering duplicating the SU\n");
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DEBUG(SU->dump(this));
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if (N->getGluedNode() &&
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!TII->canCopyGluedNodeDuringSchedule(N)) {
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DEBUG(dbgs()
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<< "Giving up because it has incoming glue and the target does not "
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"want to copy it\n");
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return nullptr;
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}
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SUnit *NewSU;
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bool TryUnfold = false;
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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MVT VT = N->getSimpleValueType(i);
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if (VT == MVT::Glue)
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if (VT == MVT::Glue) {
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DEBUG(dbgs() << "Giving up because it has outgoing glue\n");
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return nullptr;
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else if (VT == MVT::Other)
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} else if (VT == MVT::Other)
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TryUnfold = true;
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}
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for (const SDValue &Op : N->op_values()) {
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MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
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if (VT == MVT::Glue)
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if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {
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DEBUG(dbgs() << "Giving up because it one of the operands is glue and "
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"the target does not want to copy it\n");
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return nullptr;
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}
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}
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// If possible unfold instruction.
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@ -141,3 +141,16 @@ void Thumb1InstrInfo::expandLoadStackGuard(
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else
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expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
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}
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bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
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// In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
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// but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
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// even if they have glue.
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// FIXME. Actually implement the cross-copy where it is possible (post v6)
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// because these copies entail more spilling.
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unsigned Opcode = N->getMachineOpcode();
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if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
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return true;
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return false;
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}
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@ -53,6 +53,7 @@ public:
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool canCopyGluedNodeDuringSchedule(SDNode *N) const override;
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
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};
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56
test/CodeGen/Thumb/pr35836.ll
Normal file
56
test/CodeGen/Thumb/pr35836.ll
Normal file
@ -0,0 +1,56 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv5e-none-linux-gnueabi"
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; Function Attrs: norecurse nounwind optsize
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define void @f(i32,i32,i32,i32,i32* %x4p, i32* %x5p, i32* %x6p) {
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if.end:
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br label %while.body
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while.body:
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%ll.0100 = phi i64 [ 0, %if.end ], [ %shr32, %while.body ]
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%add = add nuw nsw i64 %ll.0100, 0
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%add3 = add nuw nsw i64 %add, 0
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%shr = lshr i64 %add3, 32
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%conv7 = zext i32 %0 to i64
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%conv9 = zext i32 %1 to i64
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%add10 = add nuw nsw i64 %conv9, %conv7
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%add11 = add nuw nsw i64 %add10, %shr
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%shr14 = lshr i64 %add11, 32
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%conv16 = zext i32 %2 to i64
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%conv18 = zext i32 %3 to i64
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%add19 = add nuw nsw i64 %conv18, %conv16
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%add20 = add nuw nsw i64 %add19, %shr14
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%conv21 = trunc i64 %add20 to i32
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store i32 %conv21, i32* %x6p, align 4
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%shr23 = lshr i64 %add20, 32
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%x4 = load i32, i32* %x4p, align 4
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%conv25 = zext i32 %x4 to i64
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%x5 = load i32, i32* %x5p, align 4
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%conv27 = zext i32 %x5 to i64
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%add28 = add nuw nsw i64 %conv27, %conv25
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%add29 = add nuw nsw i64 %add28, %shr23
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%shr32 = lshr i64 %add29, 32
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br label %while.body
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}
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; CHECK: adds r3, r0, r1
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; CHECK: push {r5}
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; CHECK: pop {r1}
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; CHECK: adcs r1, r1
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; CHECK: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK: ldr r2, [sp, #8] @ 4-byte Reload
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; CHECK: adds r2, r0, r2
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; CHECK: push {r5}
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; CHECK: pop {r4}
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; CHECK: adcs r4, r4
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; CHECK: adds r0, r2, r5
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; CHECK: push {r3}
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; CHECK: pop {r0}
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; CHECK: adcs r0, r4
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; CHECK: ldr r6, [sp, #4] @ 4-byte Reload
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; CHECK: str r0, [r6]
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; CHECK: ldr r0, [r7]
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; CHECK: ldr r6, [sp] @ 4-byte Reload
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; CHECK: ldr r6, [r6]
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; CHECK: adds r0, r6, r0
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57
test/CodeGen/Thumb/pr35836_2.ll
Normal file
57
test/CodeGen/Thumb/pr35836_2.ll
Normal file
@ -0,0 +1,57 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i128:64-v128:64:128-a:0:64-n64-S64"
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target triple = "thumbv6---gnueabi"
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; Function Attrs: norecurse nounwind readonly
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define i128 @a(i64* nocapture readonly %z) local_unnamed_addr #0 {
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entry:
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%0 = load i64, i64* %z, align 4
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%conv.i = zext i64 %0 to i128
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%arrayidx1 = getelementptr inbounds i64, i64* %z, i64 2
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%1 = load i64, i64* %arrayidx1, align 4
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%conv.i38 = zext i64 %1 to i128
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%shl.i39 = shl nuw i128 %conv.i38, 64
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%or = or i128 %shl.i39, %conv.i
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%arrayidx3 = getelementptr inbounds i64, i64* %z, i64 1
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%2 = load i64, i64* %arrayidx3, align 4
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%conv.i37 = zext i64 %2 to i128
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%arrayidx5 = getelementptr inbounds i64, i64* %z, i64 3
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%3 = load i64, i64* %arrayidx5, align 4
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%conv.i35 = zext i64 %3 to i128
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%shl.i36 = shl nuw i128 %conv.i35, 64
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%or7 = or i128 %shl.i36, %conv.i37
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%arrayidx10 = getelementptr inbounds i64, i64* %z, i64 4
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%4 = load i64, i64* %arrayidx10, align 4
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%conv.i64 = zext i64 %4 to i128
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%shl.i33 = shl nuw i128 %conv.i64, 64
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%or12 = or i128 %shl.i33, %conv.i
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%arrayidx15 = getelementptr inbounds i64, i64* %z, i64 5
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%5 = load i64, i64* %arrayidx15, align 4
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%conv.i30 = zext i64 %5 to i128
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%shl.i = shl nuw i128 %conv.i30, 64
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%or17 = or i128 %shl.i, %conv.i37
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%add = add i128 %or7, %or
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%add18 = add i128 %or17, %or12
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%mul = mul i128 %add18, %add
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ret i128 %mul
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}
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; CHECK: adds r4, r2, r7
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; CHECK: mov r4, r1
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; CHECK: adcs r4, r6
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; CHECK: ldr r4, [sp, #20] @ 4-byte Reload
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; CHECK: adcs r5, r4
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; CHECK: ldr r4, [sp, #24] @ 4-byte Reload
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; CHECK: adcs r3, r4
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; CHECK: adds r4, r2, r7
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; CHECK: adcs r1, r6
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; CHECK: mov r2, sp
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; CHECK: str r4, [r2]
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; CHECK: str r1, [r2, #4]
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; CHECK: ldr r6, [r0, #16]
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; CHECK: ldr r7, [r0, #24]
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; CHECK: adcs r7, r6
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; CHECK: str r7, [r2, #8]
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; CHECK: ldr r6, [r0, #20]
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; CHECK: ldr r0, [r0, #28]
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; CHECK: adcs r0, r6
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