diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 9215c17cb94..663ee15db11 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8613,7 +8613,8 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
           PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64,
           DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32));
       return DAG.getBitcast(Op.getValueType(), SplatNode);
-    } else { // We may lose precision, so we have to use XXSPLTI32DX.
+    } else if (APSplatBits.getBitWidth() == 64) {
+      // We may lose precision, so we have to use XXSPLTI32DX.
 
       uint32_t Hi =
           (uint32_t)((APSplatBits.getZExtValue() & 0xFFFFFFFF00000000LL) >> 32);
diff --git a/test/CodeGen/PowerPC/p10-splatImm32.ll b/test/CodeGen/PowerPC/p10-splatImm32.ll
index 420a96dc149..081cae729ac 100644
--- a/test/CodeGen/PowerPC/p10-splatImm32.ll
+++ b/test/CodeGen/PowerPC/p10-splatImm32.ll
@@ -100,3 +100,25 @@ define dso_local <8 x i16> @test_xxsplti32dx_9() {
 entry:
   ret <8 x i16> <i16 291, i16 undef, i16 undef, i16 364, i16 undef, i16 1, i16 173, i16 undef>
 }
+
+define dso_local <16 x i8> @test_xxsplti32dx_10() {
+; CHECK-LABEL: test_xxsplti32dx_10:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxlxor vs34, vs34, vs34
+; CHECK-NEXT:    xxsplti32dx vs34, 0, 1207959552
+; CHECK-NEXT:    blr
+entry:
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 72, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 72>
+}
+
+; FIXME: It appears that there is something wrong with the computation
+;        of the 64-bit constant to splat so we cannot emit xxsplti32dx for
+;        this test case for now.
+define dso_local <16 x i8> @constSplatBug() {
+; CHECK-LABEL: constSplatBug:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    plxv vs34, .LCPI10_0@PCREL(0), 1
+; CHECK-NEXT:    blr
+entry:
+  ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71>
+}